- Exploring the Cache Design Space for Large Scale CMPs , Ravi Iyer, Srihari Makineni, Steve Reinhardt
- Dynamic Leakage-Energy Management of Secondary Caches Erik G. Hallnor and Steven K. Reinhardt
- Abstract--As network I/O bandwidths scale up to multiple gigabits per second, the technical challenges of dealing with these
- Communist, Utilitarian, and Capitalist Cache Policies on CMPs
- Transient Fault Detection via Simultaneous Multithreading Steven K. Reinhardt
- Transient Fault Detection via Simultaneous Multithreading Steven K. Reinhardt
- Tempest and Typhoon: User-Level Shared Memory Steven K. Reinhardt, James R. Larus, and David A. Wood
- A previous evaluation of scheduled region prefetching showed that this technique eliminates the bulk of main
- Copyright 1998 IEEE. Published in IEEE Transactions on Computers, vol. 47, no. 10, Oct. 1998. Personal use of this material is permitted. However, permission to reprint/republish this material for advertising or promotional purposes or for creating new c
- 29 th Annual International Symposium on Computer Architecture (ISCA), 2002 Detailed Design and Evaluation of Redundant
- Performance Validation of Network-Intensive Workloads on a Full-System Simulator
- Design and Applications of a Virtual Context Architecture David Oehmke, Nathan Binkert, Steven Reinhardt, Trevor Mudge
- Increasing the number of instruction queue (IQ) entries in a dynamically scheduled processor exposes more
- A Unified Compressed Memory Hierarchy Erik G. Hallnor and Steven K. Reinhardt
- As DRAM access latencies approach a thousand instruction execution times and onchip caches grow to multiple megabytes, it
- The EECS 373 ``Design of Microprocessorbased Systems'' course at the University of Michigan ties
- A previous evaluation of scheduled region prefetching showed that this technique eliminates the bulk of main-
- 1 Introduction Multithreading is a wellknown technique for
- Reducing DRAM Latencies with an Integrated Memory Hierarchy Design This work is supported in part by the National Science Foundation under
- Predicting Last-Touch References under Optimal Replacement Wei-Fen Lin and Steven K. Reinhardt
- Simultaneous multithreading (SMT) increases processor throughput by multiplexing resources among several threads.
- Increasing the number of instruction queue (IQ) entries in a dynamically scheduled processor exposes more
- Analyzing NIC Overheads in Network-Intensive Workloads Nathan L. Binkert, Lisa R. Hsu, Ali G. Saidi,
- Simultaneous Subordinate Microthreading (SSMT) Robert S. Chappelly Jared Starky Sangwook P. Kimyz Steven K. Reinhardty Yale N. Patty
- PicoServer: Using 3D Stacking Technology To Enable A Compact Energy Efficient Chip Multiprocessor
- To appear in the Workshop for Memory Performance Issues 2004 A Compressed Memory Hierarchy using
- A Compressed Memory Hierarchy using an Indirect Index Cache Erik G. Hallnor and Steven K. Reinhardt
- As DRAM access latencies approach a thousand instruction-execution times and on-chip caches grow to multiple megabytes, it
- Integrated Network Interfaces for High-Bandwidth TCP/IP Nathan L. Binkert Ali G. Saidi Steven K. Reinhardt
- CSE-TR-505-04 1 Analyzing NIC Overheads in Network-Intensive Workloads
- Appears in ANCHOR '04 The Performance Potential of an Integrated Network Interface
- Full-System Critical Path Analysis Ali G. Saidi Nathan L. Binkert Steven K. Reinhardt Trevor Mudge
- Appears in: \Proceedings of the 1993 ACM SIGMETRICS Conference," May 1993. Reprinted by permission of ACM.
- 1. Introduction Radiation-induced soft errors have emerged as a key challenge
- Annual International Symposium on Computer Architecture (ISCA), 2002 Detailed Design and Evaluation of Redundant
- Simultaneous Subordinate Microthreading (SSMT) Robert S. Chappelly Jared Starky Sangwook P. Kimyz Steven K. Reinhardty Yale N. Patty
- 1 Introduction Multithreading is a well-known technique for
- Automatic Performance Setting for Dynamic Voltage Scaling May 30, 2001 1 of 12 The emphasis on processors that are both low power
- The EECS 373 "Design of Microprocessor-based Systems" course at the University of Michigan ties
- Copyright 1998 IEEE. Published in IEEE Transactions on Computers, vol. 47, no. 10, Oct. 1998. Personal use of this material is permitted. However, permission to reprint/republish this material for advertising or promotional purposes or for creating new c
- To overcome the performance cost of simulating detailed timing models, computer architects often aug-
- Appears in PACT 2005 Page 1 Current high-performance computer systems are
