- Characterizing the SPHINX Speech Recognition Kartik K. Agaram Stephen W. Keckler Doug Burger
- MIT Concurrent VLSI Architecture Memo 61 Massachusetts Institute of Technology
- A Coupled MultiALU Processing Node for a Highly Parallel Computer 1 Stephen W. Keckler
- Appears in The 1st ACM/IEEE International Symposium on Networks-on-Chip 2007. IEEE copyright restrictions apply. Implementation and Evaluation of a Dynamically
- MASSACHUSETTS Intelligence
- Appears in the Proceedings of the 2001 International Conference on Computer Design Static Energy Reduction Techniques for Microprocessor Caches
- Appears in the 21 st International Conference on Computer Design Routed InterALU Networks for ILP Scalability and Performance
- Appears in the Proceedings of the 2001 International Conference on Parallel Architectures and Compilation Techniques (PACT 2001) Exploring the Design Space of Future CMPs
- SimpleScalar Simulation of the PowerPC Instruction Set Architecture
- Appears in the Proceedings of the 6th International Conference on Architectural Support for Programming Languages and Operating Systems (ASPLOS VI).
- Appears in the 13 th International Conference on Parallel Architecture and Compilation Techniques (PACT 2004) Static Placement, Dynamic Issue (SPDI) Scheduling for EDGE Architectures
- Impact of Technology Scaling on Instruction Execution M.S. Hrishikesh Doug Burger Stephen W. Keckler
- Appears in the Proceedings of the 39th Annual IEEE/ACM International Symposium on Microarchitecture Dataflow Predication
- Appears in the 11 th International Conference on Architectural Support for Programming Languages and Operating Systems Scalable Selective ReExecution for EDGE Architectures
- Technology Independent Area and Delay Estimates for Microprocessor Building Blocks
- Appears in ICCD 2006. IEEE copyright restrictions apply. Implementation and Evaluation of On-Chip
- Appears in the 17th IEEE International Symposium on High-Performance Computer Architecture (HPCA-17) Exploiting Criticality to Reduce Bottlenecks in Distributed Uniprocessors
- Decomposing Memory Performance: Data Structures and Phases Kartik K. Agaram Stephen W. Keckler Calvin Lin Kathryn S. McKinley
- Modeling the Effect of Technology Trends on Soft Error Rate of Combinational Logic
- Appears in the Proceedings of MICRO28. The M--Machine Multicomputer
- Appears in the 36 th Annual International Symposium on Microarchitecture
- A TECHNOLOGY-SCALABLE ARCHITECTURE FOR FAST CLOCKS AND HIGH ILP
- A Coupled MultiALU Processing Node for a Highly Parallel Computer
- Appears in the Proceedings of the 14th International Symposium on Low Power Electronics and Design
- Appears in ICCD 2006. IEEE copyright restrictions apply. Design and Implementation of the TRIPS Primary
- 19.5: D. Burger Appears in the 2005 GOMACTech Intelligent Technologies Conference 19.5: Breaking the GOP/Watt Barrier with EDGE Architectures
- Appears in the 11th International Conference on Architectural Support for Programming Languages and Operating Systems Scalable Selective Re-Execution for EDGE Architectures
- Appears in the Proceedings of the Annual International Symposium on Computer Architecture
- Appears in the Proceedings of the 10 International Conference on Architectural Support for Programming Languages and Operating Systems (ASPLOS)
- Appears in the Proceedings of the 2001 International Conference on Parallel Architectures and Compilation Techniques (PACT 2001) Exploring the Design Space of Future CMPs
- Measuring Experimental Error in Microprocessor Simulation Rajagopalan Desikan+
- Appears in the International Symposium on High-Performance Computing, Tokyo, Japan, October 2000
- The Effects of Explicitly Parallel Mechanisms on the Multi-ALU Processor Cluster Pipeline Andrew Chang, William J. Dally, Stephen W. Keckler, Nicholas P. Carter, Whay S. Lee
- '90 '91 '92 '93 '94 '95 Intel Pentium
- Concurrent Event Handling through Multithreading
- 0018-9162/98/$10.00 1998 IEEE November 1998 69 n traditional message interfaces, high latency and
- Netrace: Dependency-Driven Trace-Based Network-on-Chip Simulation
- Appears in the Proceedings of the 2010 Workshop on Parallel Execution of Sequential Programs on Multi-core Architectures (PESPMA) held in conjunction with the 37th International Symposium on Computer Architecture (ISCA)
- Hybrid Operand Communication for Dataflow Dong Li Behnam Robatmili Sibi Govindan Doug Burger Steve Keckler
- Multitasking Workload Scheduling on Flexible Core Chip Multiprocessors Divya P. Gulati Changkyu Kim Simha Sethumadhavan Stephen W. Keckler
- Software Infrastructure and Tools for the TRIPS Prototype Bill Yoder Jim Burrill Robert McDonald Kevin Bush
- Exploiting Slack for Low Overhead Soft Error Reliability Premkishore Shivakumar and Stephen W. Keckler
- Appears in the Proceedings of the Annual Workshop on Optimizations for DSP and Embedded Systems Evaluation and Optimization of Signal Processing Kernels
- Power and Performance Optimization: A Case Study with the Pentium M Processor
- Appears in the Proceedings of the 2005 Workshop on High Performance Computing Reliability Issues Fault Aware Instruction Placement for Static Architectures
- Coordinated Management: Power, Performance, Energy, and Temperature
- Exploiting Microarchitectural Redundancy For Defect Tolerance Premkishore Shivakumar Stephen W. Keckler Charles R. Moore Doug Burger
- Appears in the Proceedings of the 2002 International Conference on Dependable Systems and Networks Modeling the Effect of Technology Trends on the
- Appears in the Proceedings of the 34 Annual International Symposium on Microarchitecture A Design Space Evaluation of Grid Processor Architectures
- Appears in the Proceedings of the 29 th International Symposium on Computer Architecture The Optimal Logic Depth Per Pipeline Stage is 6 to 8 FO4 Inverter Delays
- Appears in the Proceedings of the 33 Annual International Symposium on Microarchitecture
- Appears in the Proceedings of the 25th Annual International Symposium on Computer Architecture. Exploiting FineGrain Thread Level
- Appears in the Proceedings of the 30 th Annual International Symposium on Computer Architecture Exploiting ILP, TLP, and DLP with the Polymorphous TRIPS Architecture
- Appears in the Proceedings of the 25th Annual International Symposium on Computer Architecture. Exploiting Fine--Grain Thread Level
- 9.6 A Wire-Delay Scalable Microprocessor Architecture for High Performance Systems Stephen W. Keckler+, Doug Burger+, Charles R. Moore+, Ramadass Nagarajan+, Karthikeyan Sankaralingam+, Vikas
- Power and Thermal Characteristics of a Pentium M System Heather Hanson
- Fast Thread Communication and Synchronization Mechanisms for a Scalable Single Chip Multiprocessor
- Appears in the Proceedings of the 27 th Annual International Symposium on Computer Architecture Clock Rate versus IPC: The End of the Road for
- Appears in the 2011 IEEE International Symposium on Performance Analysis of Systems and Software (ISPASS) Evaluation and Optimization of Multicore Performance Bottlenecks in
- Appears in the Proceedings of MICRO-28. The MMachine Multicomputer
- Thermal Response to DVFS: Analysis with an Intel Pentium M
- Multitasking Workload Scheduling on Flexible-Core Chip Multiprocessors
- Late-Binding: Enabling Unordered Load-Store Queues Simha Sethumadhavan
- Appears in the Proceedings of the 10 th International Conference on Architectural Support for Programming Languages and Operating Systems (ASPLOS) An Adaptive, NonUniform Cache Structure for
- Appears in the Workshop on High-Performance, Power-Aware Computing (HPPAC 2007) Power, Performance, and Thermal Management for High-Performance Systems
- IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS, VOL. 11, NO. 3, JUNE 2003 303 Static Energy Reduction Techniques for
- Appears in the Proceedings of the 14th International Conference on Architecture Support for Programming Languages and Operating Systems An Evaluation of the TRIPS Computer System
- High Performance Dense Linear Algebra on a Spatially Distributed Processor
- Power, Performance, and Thermal Management for High-Performance Systems Heather Hanson1
- Appears in the Annual International Symposium on Microarchitecture Distributed Microarchitectural Protocols in the TRIPS Prototype Processor
- Appears in the Proceedings of the 27 Annual International Symposium on Computer Architecture
- Processor Coupling: Integrating Compile Time and Runtime Scheduling for Parallelism \Lambda
- Appears in the 21 st International Conference on Computer Design
- The E ect of Technology Scaling on Microarchitectural Vikas Agarwal Stephen W. Keckler Doug Burger
- The Effects of Explicitly Parallel Mechanisms on the MultiALU Processor Cluster Pipeline Andrew Chang, William J. Dally, Stephen W. Keckler, Nicholas P. Carter, Whay S. Leey
- Appears in the Proceedings of the 6th International Conference on Architectural Support for Programming Languages and Operating Systems (ASPLOS VI).
- Measuring Experimental Error in Microprocessor Simulation Rajagopalan Desikan + , Doug Burger * , and Stephen W. Keckler *
- Appears in the 36 th Annual International Symposium on Microarchitecture
- Appears in the 2009 IEEE International Symposium on Performance Analysis of Systems and Software Analysis of the TRIPS Prototype Block Predictor
- Appears in the Proceedings of the 35th Annual International Symposium on Computer Architecture
- Coordinated Power, Energy, and Temperature Management for High-Performance Microprocessors
- Appears in the Value-Prediction Workshop
- Appears in the 2006 IEEE International Symposium on Performance Analysis of Systems and Software (ISPASS 2006) Critical Path Analysis of the TRIPS Architecture
- Processor Coupling: Integrating Compile Time and Runtime Scheduling for Parallelism
- Appears in the Proceedings of the 4 th Annual Workshop on Workload Characterization A Characterization of Speech Recognition on Modern Computer Systems
- Microprocessor Pipeline Energy Analysis Karthik Natarajan , Heather Hanson , Stephen W. Keckler, Charles R. Moore, Doug Burger
- Appears in the Proceedings of the 38th International Symposium on Computer Architecture
- A Compile-Time Managed Multi-Level Register File Mark Gebhart1
