- Graph-Based Algorithms for Boolean Function Manipulation12
- Optimizing Symbolic Model Checking for Constraint-Rich Models
- Verification of Arithmetic Functions with Binary Moment Diagrams
- Indexed Predicate Discovery for Unbounded System Verification #
- Copyright 1998 IEEE. Published in the Proceedings of CSD'98, March 1998 Fukushima, Japan. Personal use of this material is permitted. However, permission to reprint/republish this material for advertising or promotional purposes or for creating
- Article Submitted to Journal of Symbolic Computation E ective Use of Boolean Satis ability
- On the Complexity of VLSI Implementations and Graph Representations of Boolean Functions
- Symbolic Manipulation of Boolean Functions Using a Graphical Representation
- Formal Verification of a Superscalar Execution Unit 1 Kyle L. Nelson Alok Jain Randal E. Bryant
- Mapping switch-level simulation onto gate-level hardware accelerators Alok Jain
- EVC: A Validity Checker for the Logic of Equality with Uninterpreted Functions and Memories, Exploiting
- Boolean Satisfiability with Transitivity Constraints ? Randal E. Bryant 1 and Miroslav N. Velev 2
- Formal Verification of an ARM processor Vishnu A. Patankar Alok Jain Randal E. Bryant
- Copyright 1998 IEEE. Published in the Proceedings of ICCD'98, 57 October 1998 in Austin, Texas. Personal use of this material is per mitted. However, permission to reprint/republish this material for advertising or promotional purposes or for creating new
- Formal Hardware Verification by Symbolic Ternary Trajectory Evaluation #
- Processor Veri cation Using Ecient Reductions of the Logic of Uninterpreted Functions to
- CMOS Circuit Verification with Symbolic SwitchLevel Timing Simulation
- IEEE TRANSACTIONS ON COMPUTER AIDED DESIGN, VOL. XX, NO. Y, MONTH 1999 1 Exploiting symmetry when verifying transistorlevel
- Appears in the proceedings of Asian Computer Science Conference (ASIAN '97), R.K. Shyamasundar and K. Ueda, eds., LNCS 1345, SpringerVerlag, December 1997, pp. 1831.
- Boolean Analysis of MOS Circuits \Lambda Randal E. Bryant
- Guided Symbolic Universal Planning Rune M. Jensen, Manuela M. Veloso and Randal E. Bryant
- Formal Verification by Symbolic Evaluation of PartiallyOrdered Trajectories \Lambda
- Formal Verification of Infinite State Systems Using Boolean Methods #
- Our goal is to transform a lowlevel circuit design into a more abstract representation. A preexisting tool, Tranalyze [4], takes a
- Symbolic Simulation---Techniques and Applications \Lambda Randal E. Bryant
- System Modeling and Verification with UCLID Randal E. Bryant
- Symbolic Simulation, Model Checking and Abstraction with Partially Ordered Boolean
- Symbolic Functional and Timing Verification of TransistorLevel Circuits Clayton B. McDonald and Randal E. Bryant \Lambda
- Deciding QuantifierFree Presburger Formulas Using Parameterized Solution Sanjit A. Seshia Randal E. Bryant
- A Hybrid SATBased Decision Procedure for Separation Logic with Uninterpreted Functions #
- Binary Decision Diagrams and Beyond: Enabling Technologies for Formal Verification \Lambda
- Algorithmic Aspects of Symbolic Switch Network Analysis \Lambda
- An Ecient Graph Representation for Arithmetic Circuit Veri cation
- Symbolic Analysis Methods for Masks, Circuits, and Systems
- FormalVerification of Superscalar Microprocessors with Multicycle Functional Units, Exceptions, and Branch Prediction 1
- Symbolic Representation with Ordered Function Templates Department of Electrical &
- Formal Verification of Memory Circuits by SwitchLevel Simulation \Lambda
- Computing LogicStage Delays Using Circuit Simulation and Symbolic Elmore Analysis
- To appear in the proceedings of FMCAD '98, G.C. Gopalakrishnan and P.J. Windley, eds., November 1998. BitLevel Abstraction in the Verification of Pipelined
- Formal Verification of Digital Circuits Using Symbolic Ternary System Models \Lambda
- Effective Use of Boolean Satisfiability Procedures in the Formal Verification of Superscalar and VLIW Microprocessors 1
- Formal Verification of Infinite State Systems Using Boolean Methods # Randal E. Bryant
- Extraction of Finite State Machines from Transistor Netlists by Symbolic Simulation \Lambda
- Symbolic Boolean Manipulation with Ordered Binary Decision Diagrams
- Modeling and Verifying Systems using a Logic of Counter Arithmetic with Lambda Expressions
- Modeling and Veri cation of Out-of-Order Microprocessors in UCLID
- Semantics-Aware Malware Detection Mihai Christodorescu
- To appear in the proceedings of the 36th Design Automation Conference (DAC'99), June 1999. Exploiting Positive Equality and Partial Non-Consistency
- Symbolic Representation with Ordered Function Templates Department of Electrical &
- Geometric Characterization of SeriesParallel Variable Resistor Networks # Randal E. Bryant
- Digital Circuit Verification using PartiallyOrdered State Models \Lambda
- A Methodology for Hardware Verification Based on Logic Simulation \Lambda
- Predicate Abstraction with Indexed Predicates SHUVENDU K. LAHIRI
- Data Parallel SwitchLevel Simulation \Lambda Randal E. Bryant
- Appears in the proceedings of Correct Hardware Design and Verification Methods (CHARME `99), L. Pierre and T. Kropf, eds., LNCS 1703, SpringerVerlag, September 1999, pp. 3753.
- Symbolic Verification of MOS Circuits 1 Randal E. Bryant 2
- To appear at ASYNC'05 Modeling and Verifying Circuits Using Generalized Relative Timing
- Unbounded, Fully Symbolic Model Checking of Timed Automata using Boolean Methods
- Symbolic Timing Simulation Using Cluster Scheduling Clayton B. McDonald Randal E. Bryant \Lambda
- Verification of Arithmetic Circuits with Binary Moment Diagrams \Lambda
- Verifying Nondeterministic Implementations of Deterministic Systems 1
- Test Pattern Generation for Sequential MOS Circuits
- ACV: An Arithmetic Circuit Verifier \Lambda YirngAn Chen Randal E. Bryant
- Verification of Synchronous Circuits by Symbolic Logic Simulation
- Geometric Characterization of SeriesParallel Variable Resistor Networks #
- GraphBased Algorithms for Boolean Function Manipulation 12
- To appear in the First International Conference on Tools and Algorithms for the Construction and Analysis of Systems (TACAS '98), Portugal, MarchApril 1998.
- BitLevel Analysis of an SRT Divider Circuit \Lambda Randal E. Bryant
- Appears in the proceedings of ComputerAided Verification `97, O. Grumberg, ed., LNCS 1254, SpringerVerlag, June 1997, pp. 388399.
- Extraction of Gate Level Models from Transistor Circuits by FourValued Symbolic Analysis
- A Compiled Simulator for MOS Circuits \Lambda Randal E. Bryant
- Formal verification of PowerPC TM arrays using symbolic trajectory evaluation \Lambda Manish Pandey 1 Richard Raimi 2 Derek L. Beatty 2 Randal E. Bryant 1
- Set Manipulation with Boolean Functional Vectors for Symbolic Reachability Analysis
- Space and TimeEfficient BDD Construction via Working Set Control Bwolen Yang \Lambda YirngAn Chen y Randal E. Bryant y David R. O'Hallaron \Lambda
- Verification of FloatingPoint Adders ?? YirngAn Chen and Randal E. Bryant
- An Efficient BDDBased A* Algorithm Rune M. Jensen, Randal E. Bryant, and Manuela M. Veloso
- SetA*: An Efficient BDDBased Heuristic Search Algorithm Rune M. Jensen, Randal E. Bryant, and Manuela M. Veloso
- Boolean Satisfiability with Transitivity Constraints RANDAL E. BRYANT
- Exploiting symmetry when verifying transistorlevel circuits by symbolic trajectory
- To appear in the proceedings of the 36th Design Automation Conference (DAC'99), June 1999. Exploiting Positive Equality and Partial NonConsistency
- Software Tools for Technology Transfer manuscript No. (will be inserted by the editor)
- FORMAL METHODS FOR FUNCTIONAL VERIFICATION
- An Analysis of U.S. Patent #5,243,538 ``Comparison and Verification System
- A Performance Study of BDDBased Model Checking
- Deductive Veri cation of Advanced Out-of-Order Microprocessors ?
- *PHDD: An Efficient Graph Representation for Floating Point Circuit Verification y YirngAn Chen Randal E. Bryant
- Optimizing Symbolic Model Checking for ConstraintRich Models
- Exploiting Positive Equality in a Logic of Equality with Uninterpreted Functions ?
- Revisiting Positive Equality ? Shuvendu K. Lahiri, Randal E. Bryant, Amit Goel, and Muralidhar Talupur
- Symbolic Analysis Methods for Masks, Circuits, and Systems
- Our goal is to transform a low-level circuit design into a more abstract representation. A pre-existing tool, Tranalyze [4], takes a
- Term-Level Verification of a Pipelined CISC Microprocessor
- An Analysis of U.S. Patent #5,243,538 "Comparison and Verification System
- Guided Symbolic Universal Planning Rune M. Jensen, Manuela M. Veloso and Randal E. Bryant
- Predicate Abstraction with Indexed Predicates SHUVENDU K. LAHIRI
- EVC: A Validity Checker for the Logic of Equality with Uninterpreted Functions and Memories, Exploiting
- Formal Verification of Digital Circuits Using Symbolic Ternary System Models
- Verification of Arithmetic Functions with Binary Moment Diagrams \Lambda
- Symbolic Manipulation of Boolean Functions Using a Graphical Representation
- Appears in the proceedings of Computer-Aided Verification `97, O. Grumberg, ed., LNCS 1254, Springer-Verlag, June 1997, pp. 388-399.
- Constructing Quantified Invariants via Predicate Abstraction ?
- Symbolic Verification of MOS Circuits1 Randal E. Bryant2
- !#"%$'&()"0 1234&5 &6$7'&6" 8@9BADCE9BFHGPIEQSRUTV9BAVW
- Logical Methods in Computer Science Vol. 1 (2:6) 2005, pp. 126
- Boolean Satisfiability with Transitivity Constraints RANDAL E. BRYANT
- [Malik et al 1988] Malik, S., Wang, A., Brayton, R. K., and Sangiovanni-Vincentelli, A. 1988. Logic verification using binary decision diagrams in a logic synthesis environment. In-
- Automatic Discovery of API-Level Exploits Vinod Ganapathy
- To appear at ASYNC'05 Modeling and Verifying Circuits Using Generalized Relative Timing
- Indexed Predicate Discovery for Unbounded System Verification
- Deciding Quantifier-Free Presburger Formulas Using Parameterized Solution Sanjit A. Seshia Randal E. Bryant
- Constructing Quantified Invariants via Predicate Abstraction
- A Hybrid SAT-Based Decision Procedure for Separation Logic with Uninterpreted Functions
- Set Manipulation with Boolean Functional Vectors for Symbolic Reachability Analysis
- Computing Logic-Stage Delays Using Circuit Simulation and Symbolic Elmore Analysis
- Effective Use of Boolean Satisfiability Procedures in the Formal Verification of Superscalar and VLIW Microprocessors1
- Boolean Satisfiability with Transitivity Constraints Randal E. Bryant
- Symbolic Timing Simulation Using Cluster Scheduling Clayton B. McDonald Randal E. Bryant
- FormalVerificationofSuperscalarMicroprocessorswith Multicycle Functional Units, Exceptions, and Branch Prediction1
- Appears in the proceedings of Correct Hardware Design and Verification Methods (CHARME `99), L. Pierre and T. Kropf, eds., LNCS 1703, Springer-Verlag, September 1999, pp. 37-53.
- Exploiting Positive Equality in a Logic of Equality with Uninterpreted Functions
- Formal Verification of an ARM processor Vishnu A. Patankar Alok Jain Randal E. Bryant
- To appear in the proceedings of FMCAD '98, G.C. Gopalakrishnan and P.J. Windley, eds., November 1998. Bit-Level Abstraction in the Verification of Pipelined
- Copyright 1998 IEEE. Published in the Proceedings of ICCD'98, 5-7 October 1998 in Austin, Texas. Personal use of this material is per-mitted. However, permission to reprint/republish this material for advertising or promotional purposes or for creating ne
- Verification of Floating-Point Adders Yirng-An Chen and Randal E. Bryant
- Space-and Time-Efficient BDD Construction via Working Set Control Bwolen Yang
- *PHDD: An Efficient Graph Representation for Floating Point Circuit Verification Yirng-An Chen Randal E. Bryant
- ACV: An Arithmetic Circuit Verifier Yirng-An Chen Randal E. Bryant
- Verifying Nondeterministic Implementations of Deterministic Systems1
- Binary Decision Diagrams and Beyond: Enabling Technologies for Formal Verification
- Extraction of Finite State Machines from Transistor Netlists by Symbolic Simulation
- Verification of Arithmetic Circuits with Binary Moment Diagrams
- Extraction of Gate Level Models from Transistor Circuits by Four-Valued Symbolic Analysis
- A View from the Engine Room: Computational Support for Symbolic Model Checking
- Formal Verification of Infinite State Systems Using Boolean Methods Randal E. Bryant
- Formal Verification of Infinite State Systems Using Boolean Methods
- Copyright 1998 IEEE. Published in the Proceedings of CSD'98, March 1998 Fukushima, Japan. Personal use of this material is permitted. However, permission to reprint/republish this material for advertising or promotional purposes or for creating
- Bit-Level Analysis of an SRT Divider Circuit Randal E. Bryant
- An Efficient BDD-Based A* Algorithm Rune M. Jensen, Randal E. Bryant, and Manuela M. Veloso
- Formal Verification of a Superscalar Execution Unit1 Kyle L. Nelson Alok Jain Randal E. Bryant
- Symbolic Simulation, Model Checking and Abstraction with Partially Ordered Boolean
- Digital Circuit Verification using Partially-Ordered State Models
- Formal Verification of Memory Circuits by Switch-Level Simulation
- Inverter Minimization in Multi-Level Logic Networks Department of ECE
- Accepted Manuscript State-Set Branching: Leveraging BDDs for Heuristic Search
- Introducing Computer Systems from a Programmer's Perspective
- Journal on Satisfiability, Boolean Modeling and Computation N (2007) xx-yy On Solving Boolean Combinations of UTVPI Constraints
- 134 Int. J. Embedded Systems, Vol. 1, Nos. 1/2, 2005 Copyright 2005 Inderscience Enterprises Ltd.
- To appear in the First International Conference on Tools and Algorithms for the Construction and Analysis of Systems (TACAS '98), Portugal, March-April 1998.
- ATLAS: Automatic Term-Level Abstraction of RTL Designs
- Appears in the proceedings of Asian Computer Science Conference (ASIAN '97), R.K. Shyamasundar and K. Ueda, eds., LNCS 1345, Springer-Verlag, December 1997, pp. 18-31.
- Formal verification of PowerPCTM arrays using symbolic trajectory evaluation
- Symbolic Functional and Timing Verification of Transistor-Level Circuits Clayton B. McDonald and Randal E. Bryant
- Symbolic Simulation--Techniques and Applications Randal E. Bryant
- Randal E. Bryant Publications
- SetA*: An Efficient BDD-Based Heuristic Search Algorithm Rune M. Jensen, Randal E. Bryant, and Manuela M. Veloso
- Deciding Bit-Vector Arithmetic with Abstraction
- Learning Conditional Abstractions Bryan A. Brady1
