- Dynamic Capacity-Speed Tradeoffs in SMT Processor Caches
- Localized Microarchitecture-Level Voltage YongKang Zhu
- Enabling Parallelization via a Reconfigurable Chip Multiprocessor
- Phastlane: A Rapid Transit Optical Routing Network Mark J. Cianchetti, Joseph C. Kerekes, and David H. Albonesi
- Dynamically Matching ILP Characteristics Via a Heterogeneous Clustered Microarchitecture
- Scalable Thread Scheduling and Global Power Management for Heterogeneous Many-Core Architectures
- Adaptive Cache Memories for SMT Processors
- Dynamic Power Redistribution in Failure Prone CMPs Paula Petrica
- SHARED RECONFIGURABLE ARCHITECTURES FOR CMPS Matthew A. Watkins, Mark J. Cianchetti, and David H. Albonesi
- IEEE JOURNAL OF SELECTED TOPICS IN QUANTUM ELECTRONICS, VOL. 12, NO. 6, NOVEMBER/DECEMBER 2006 1699 On-Chip Optical Interconnect Roadmap: Challenges
- Synergistic Temperature and Energy Management in GALS Processor Architectures
- On-Chip Copper-Based vs. Optical Interconnects: Delay Uncertainty, Latency, Power, and Bandwidth Density Comparative Predictions
- Exploiting Coarse-Grain Verification Parallelism for Power-Efficient Fault Tolerance
- QUILT: A GUI-based Integrated Circuit Floorplanning Environment for Computer Architecture Research and Education
- Panel Discussion Micro Architecture at Santa Cruz Jose Renau
- Lost in the Bermuda Triangle:Lost in the Bermuda Triangle: Complexity vs. Energy vs. PerformanceComplexity vs. Energy vs. Performance
- Addressing Thermal Nonuniformity in SMT Workloads
- On-chip Optical Interconnect Roadmap: Challenges and Critical Directions Mikhail Haurylau, Hui Chen, Jidong Zhang, Guoqing Chen, Nicholas A. Nelson,
- Electrical and Optical On-Chip Interconnects in Scaled Microprocessors Guoqing Chen, Hui Chen, Mikhail Haurylau, Nicholas Nelson, David Albonesi, Philippe M. Fauchet, and Eby G. Friedman
- Each year, our colleagues in the com-puter architecture research community pro-
- The quest for higher performance via deep pipelining (for high clock rate) and
- Scheduling Algorithms for Unpredictably Heterogeneous CMP Architectures
- WCED Program 8:00-8:30AM Breakfast
- Dynamically Managed Multithreaded Reconfigurable Architectures for Chip Multiprocessors
- Predictions of CMOS Compatible On-Chip Optical Interconnect Guoqing Chen, Hui Chen, Mikhail Haurylau, Nicholas Nelson
- IBM Research 06/18/06 | Workshop on Complexity-Effective Design 2002 IBM Corporation
- Lost in the Bermuda Triangle: Energy, Complexity, and Performance
- Alleviating Thermal Constraints While Maintaining Performance Via Silicon-Based On-Chip Optical Interconnects
- Leveraging Optical Technology in Future Bus-based Chip Multiprocessors
- Partitioning Multi-Threaded Processors with a Large Number of Threads Ali El-Moursy , Rajeev Garg , David H. Albonesi
- Held in conjunction with the 33rd International Symposium Dave Albonesi, Cornell University
- A High Performance, Energy Efficient GALS Processor Microarchitecture with Reduced Implementation Complexity
- Dynamically Trading Frequency for Complexity in a GALS Microprocessor Steven Dropsho, Greg Semeraro, David H. Albonesi, Grigorios Magklis, and Michael L. Scott
- ReMAP: A Reconfigurable Heterogeneous Multicore Architecture Matthew A. Watkins and David H. Albonesi
- Compatible Phase Co-Scheduling on a CMP of Multi-Threaded Processors
- Question Mean Count 1 2 3 4 5 Semester: Spring 2011
- Question Mean Count 1 2 3 4 5 Semester: Fall 2010
- Question Mean Count 1 2 3 4 5 Semester: Spring 2010
- Question Mean Count 1 2 3 4 5 Semester: Fall 2011
