- High-Level Specification and Automatic Generation of IP Interface Monitors
- High-Level Cycle-Accurate Speci cation of Microprocessors
- SPUDD: Stochastic Planning using Decision Diagrams Jesse Hoey Robert St-Aubin Alan Hu Craig Boutilier
- SemiFormal Bounded Model Checking ? Jesse D. Bingham and Alan J. Hu
- Automatic Inference of Frame Axioms Using Static Analysis Zvonimir Rakamaric, Alan J. Hu
- A Scalable Memory Model for Low-Level Code Zvonimir Rakamaric and Alan J. Hu
- Generating Monitor Circuits for SimulationFriendly GSTE Assertion Graphs # Department of Computer Science
- Automatable Verification of Sequential Consistency [Extended Abstract]
- Boosting Verification by Automatic Tuning of Decision Procedures
- Structural Abstraction of Software Verification Conditions
- An Inference-Rule-Based Decision Procedure for Verification of Heap-Manipulating Programs with
- Automatic Verification of Sequential Consistency for Unbounded Addresses and Data Values
- Efficient Generation of Monitor Circuits for GSTE Assertion Graphs
- Semi-Formal Bounded Model Checking Jesse D. Bingham and Alan J. Hu
- Automatable Verification of Sequential Consistency [Extended Abstract]
- Static and Precise Detection of Concurrency Errors in Systems Code Using SMT Solvers
- Partitioned Model Checking from Software Specifications # Xiushan Feng
- Automatic Formal Verification for Scheduled VLIW Code Xiushan Feng
- Automatic Formal Verification of DSP Software David W. Currie +
- Integration of Supercubing and Learning in a SAT Solver Domagoj Babic and Alan J. Hu
- Fast Specification of CycleAccurate Processor Models Felix ShengHo Chang and Alan J. Hu
- Empirically Efficient Verification for a Class of InfiniteState Systems #
- Formal Verification of DSP Assembly Language David W. Currie
- Proving Sequential Consistency by Model Checking Tim Braun + , Anne Condon , Alan J. Hu , Kai S. Juse + , Marius Laza , Michael Leslie # , and Rita Sharma
- B-Cubing Theory: New Possibilities for Efficient SAT-Solving Domagoj Babic, Jesse Bingham, and Alan J. Hu
- High-Level Specification and Automatic Generation of IP Interface Monitors
- Automatic Verification of Sequential Consistency for Unbounded Addresses and Data Values #
- Satis ability Suggested Format
- BDDNOW: A Parallel BDD Package Kim MilvangJensen
- HighLevel Specification and Automatic Generation of IP Interface Monitors
- Formal Hardware Verification with BDDs: An Introduction \Lambda Department of Computer Science
- ModelChecking A Secure Group Communication Protocol: A Case Study
- High-Level vs. RTL Combinational Equivalence: An Introduction
- Toward A Decidable Notion of Sequential Consistency # Jesse D. Bingham
- Empirically Efficient Verification for a Class of Infinite-State Systems
- Early Cutpoint Insertion for High-Level Software vs. RTL Formal Combinational Equivalence Verification
- An Effective Guidance Strategy for Abstraction-Guided Simulation Flavio M. De Paula Alan J. Hu
- Efficient SAT Solving: Beyond Supercubes Domagoj Babic Jesse Bingham Alan J. Hu
- BDDNOW: A Parallel BDD Package ? Kim MilvangJensen 1 and Alan J. Hu 2
- Cutpoints for Formal Equivalence Verification of Embedded Software
- Efficient Generation of Monitor Circuits for GSTE Assertion Graphs
- Register Transformations with Multiple Clock Domains ? Alvin R. Albrecht and Alan J. Hu
- Formal Verification of the HAL S1 System Cache Coherence Protocol
- Reasoning about GSTE Assertion Graphs Alan J. Hu 1 , Jeremy Casas 2 , and Jin Yang 2
- SourceLevel Transformations for Improved Formal Verification Brian D. Winters and Alan J. Hu
- BCubing Theory: New Possibilities for Efficient SATSolving # Domagoj Babic, Jesse Bingham, and Alan J. Hu
- Cutpoints for Formal Equivalence Verification of Embedded Software #
- TECHNIQUES FOR EFFICIENT FORMAL VERIFICATION
- EverLost: A Flexible Platform for Industrial-Strength Abstraction-Guided Simulation
- Verifying Heap-Manipulating Programs in an SMT Framework
