Harris, Ian G. - Department of Electrical and Computer Engineering, University of California, Irvine

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Harris, Ian G. - Department of Electrical and Computer Engineering, University of California, Irvine

Partial BIST Insertion to Eliminate Data Correlation A new partial BIST insertion approach based on eliminating
*tick, paid=5||10||15 -> *pump, pump=5||10||15
Testing and Diagnosis of Interconnect Faults in Cluster-Based FPGA Architectures
A Validation Fault Model for Timing-Induced Functional Errors Qiushuang Zhang and Ian G. Harris
Partial BIST Insertion to Eliminate Data Correlation Qiushuang Zhang and Ian Harris
Reconvergent Fanout Removal Through Partial BIST Insertion Ian G. Harris
Eliminating Nondeterminism to Enable Chip-Level Test of Globally-Asynchronous Locally-Synchronous SoC's
Diagnosis of Interconnect Faults in Cluster-Based FPGA Architectures
Mutation Analysis for the Evaluation of Functional Fault Models Qiushuang Zhang and Ian Harris
A Deterministic Globally Asynchronous Locally Synchronous Microprocessor Architecture
Fault Models and Test Generation for Hardware-Software Covalidation Ian G. Harris
TEST GENERATION FOR HARDWARE-SOFTWARE COVALIDATION USING NON-LINEAR PROGRAMMING
ATPG for Timing-Induced Functional Errors on Trigger Events in Hardware-Software Systems