- The general purpose processor has long been the focus of intense optimization efforts that have resulted in an
- To appear in the Proceedings of the 36th Annual International Symposium on Microarchitecture (MICRO), December 2003
- A critical concern for embedded sys-tems is the need to deliver high levels of per-
- IF ID REN R O B CT out-of-order
- High-Bandwidth Address Translation for Multiple-Issue Processors
- In Proceedings of the 4th International Symposium on High Performance Computing (ISHPC), May 2002, (c) Springer-Verlag. High Performance and Energy Efficient Serial Prefetch Architecture
- In Proceedings of the 32nd Annual International Symposium on Microarchitecture (MICRO-32), November 1999. Fetch Directed Instruction Prefetching
- Software-Based Online Detection of Hardware Defects: Mechanisms, Architectural Support, and Evaluation
- Fault-Based Attack of RSA Authentication Andrea Pellegrini, Valeria Bertacco and Todd Austin
- IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS, VOL. 17, NO. 8, AUGUST 2009 1127 Energy-Efficient Subthreshold Processor Design
- A Flexible Software-Based Framework for Online Detection of Hardware Defects
- Performance and Variability Optimization Strategies in a Sub-200mV, 3.5pJ/inst, 11nW Subthreshold Processor
- Ultra Low-Cost Defect Protection for Microprocessor Pipelines Smitha Shyam Kypros Constantinides Sujay Phadke
- A 2.60pJ/Inst Subthreshold Sensor Processor for Optimal Energy Efficiency Bo Zhai, Leyla Nazhandali, Javin Olson, Anna Reeves, Michael Minuth, Ryan Helfand,
- BulletProof: A Defect-Tolerant CMP Switch Architecture Kypros Constantinides
- Depth-Driven Verification of Simultaneous Interfaces Ilya Wagner Valeria Bertacco Todd Austin
- Deployment of Better Than Worst-Case Design: Solutions and Needs Todd Austin Valeria Bertacco
- A Second-Generation Sensor Network Processor with Application-Driven Memory Optimizations
- StressTest: An Automatic Approach to Test Generation Via Activity Monitors
- Recently, a new Dynamic Voltage Scaling (DVS) scheme has been proposed that increases energy efficiency
- DVS for On-Chip Bus Designs Based on Timing Error Correction Himanshu Kaul
- Opportunities and Challenges for Better Than Worst-Case Design Todd Austin, Valeria Bertacco, David Blaauw and Trevor Mudge
- Designing Robust Microarchitectures Todd M. Austin
- May 2004 81 E M B E D D E D C O M P U T I N G
- With increasing clock frequencies and silicon integration, power aware computing has become a critical concern in the design
- Improperly bounded program inputs present a major class of program defects. In secure applications, these bugs can
- Appears in ISPASS-2001. MASE: A Novel Infrastructure for Detailed Microarchitectural Modeling
- Appears in the 28th Annual International Symposium on Computer Architecture (ISCA-2001), June 2001
- Architectural Support for Fast Symmetric-Key Cryptography Jerome Burke John McDonald Todd Austin
- 90272-1732/99/$10.00 1999 IEEE Today's methodology for designing
- Zero-Cycle Loads: Microarchitecture Support for Reducing Load Latency
- Streamlining Data Cache Access with Fast Address Calculation
- Assessing SEU Vulnerability via Circuit-Level Timing Analysis
- The use of simulation is well established in academic and industry research as a means of
- This paper examines a set of commercially representative embedded programs and compares them
- MASE: A Novel Infrastructure for Detailed Microarchitectural Modeling Advanced Computer Architecture Laboratory
- E cient Detection of All Pointer and Array Access Errors Todd M. Austin Scott E. Breach Gurindar S. Sohi
- Appears in Dependable Systems and Networks (DSN), July 2001 We propose a fault-tolerant approach to reliable micropro-
- The SimpleScalar Tool Set, Version 2.0 *Contact: dburger@cs.wisc.edu
- Polymorphic On-Chip Networks Martha Mercaldi Kim
- Published in the Proceedings of the 26th International Symposium on Computer Architecture, May 1999. A Scalable Front-End Architecture for Fast Instruction Delivery
- The Last Byte The pecking order in most design teams is
- Permission to make digital or hard copies of all or part of this work for personal or classroom use is granted without fee provided that copies are
- Dynamic Dependency Analysis of Ordinary Programs 1 Todd M. Austin and Gurindar S. Sohi
- Exploiting Selective Placement for Low-cost Memory Protection
- Dynamic Hammock Predication for Non-predicated Instruction Set Architectures
- Cache accesses consume a significant portion of total energy dissipation in modern microprocessors. In this paper, we introduce
- Copyright 1997 IEEE. Published in the Proceedings of Micro-30, December 1-3, 1997 in Research Triangle Park, North Carolina. Per-sonal use of this material is permitted. However, permission to reprint/republish this material for advertising or promotional
- Appears in MICRO-33 Compiler Controlled Value Prediction using Branch Predictor Based Confidence
- HARDWARE AND SOFTWARE MECHANISMS FOR REDUCING LOAD LATENCY
- International Journal of Parallel Programming , Vol . 27, No. 5, 1999 Memory Renaming: Fast, Early and
- SimpleDSP: A Fast and Flexible DSP Processor Model (EXTENDED ABSTRACT)
- The trend towards deeper microprocessor pipelines has made it advantageous or necessary to predict the
- Copyright 1997 IEEE. Published in the Proceedings of Micro-30, December 1-3, 1997 in Research Triangle Park, North Carolina. Personal use of thismaterial is permitted. However, permission to reprint/republish this material
- Remora: A Dynamic Self-Tuning Processor Chris Weaver, Fadi Gebara, Todd Austin, and Richard Brown
- Energy Optimization of Subthreshold-Voltage Sensor Network Processors
- 0018-9162/02/$17.00 2002 IEEE February 2002 59 C O V E R F E A T U R E
- To achieve high instruction throughput, instruction schedulers must be capable of producing high-quality
- High-end microprocessors are increasing in complex-ity to push the limits of speed and performance. As a result,
- An increasingly large portion of scheduler latency is derived from the monolithic content addressable memory
- Optimizations Enabled by a Decoupled Front-End Architecture
- IEEE JOURNAL OF SOLID-STATE CIRCUITS, VOL. 43, NO. 4, APRIL 2008 881 Exploring Variability and Performance
- Circuit-Aware Architectural Simulation Seokwoo Lee, Shidhartha Das, Valeria Bertacco, Todd Austin
- T E C H N O L O G Y I N -D E P T H Volume 3, Number 4, 2004Information Quarterly [30]
- The continuous exponential growth in transistors per chip as described by Moore's
- Memory System Design Space Exploration for Low-Power, Real-Time Speech Recognition
- E cient Detection of All Pointer and Array Access Errors Todd M. Austin Scott E. Breach Gurindar S. Sohi
- 0018-9162/04/$20.00 2004 IEEE March 2004 57 C O V E R F E A T U R E
- Architecting a Reliable CMP Switch Architecture
- SenseBench: Toward an Accurate Evaluation of Sensor Network Processors
- Fault-Based AttackFault Based Attack of RSA Authentication
- The design and implementation of a modern micro-processor creates many reliability challenges. Design-
- A Self-Tuning DVS Processor Using Delay-Error Detection and Correction Shidhartha Das, Sanjay Pant, David Roberts, Seokwoo Lee, David Blaauw, Todd Austin, Trevor Mudge, Krisztian Flautner*
- Shielding Against Design Flaws with Field Repairable Control Logic
- Low-cost Protection for SER Upsets and Silicon Defects Mojtaba Mehrara Mona Attariyan Smitha Shyam Kypros Constantinides
- Reliable Systems on Unreliable Fabrics
- Classifying Load and Store Instructions for Memory Renaming Glenn Reinmany Brad Caldery Dean Tullseny Gary Tysonz Todd Austin
- Published in the Proceedings of the 32nd International Symposium on Microarchitecture, November 1999. DIVA: A Reliable Substrate for
- Efficient Software Decoder Design Rajeev Krishna, Todd Austin
- Evaluating Future Microprocessors: the SimpleScalar Tool Set Doug Burger*
- 1126 IEEE TRANSACTIONS ON COMPUTER-AIDED DESIGN OF INTEGRATED CIRCUITS AND SYSTEMS, VOL. 26, NO. 6, JUNE 2007 Microprocessor Verification via
- High-end microprocessors continue to increase in complexity to push the limits of speed and performance.
- Cache-Conscious Data Placement Brad Calder Chandra Krintz Simmi John Todd Austin
