- Full-System Timing-First Carl J. Mauer
- The Wisconsin Wind Tunnel Project: An Annotated Bibliography
- To Appear in the Proceedings of the 18th Annual International Symposium on Computer Architecture Detecting Data Races on Weak Memory Systems
- Fast Checkpoint/Recovery to Support Kilo-Instruction Speculation and Hardware Fault Tolerance
- This work is supported in part by the National Science Foundation with grants MIP-9225097, MIPS-9625558, CCR 9257241, and CDA-9623632,
- Slack: Maximizing Performance Under Technological Constraints Brian Fields Rastislav Bodik Mark D. Hill
- This work is supported in part by Wright Laboratory Avionics Directorate, Air Force Material Command, USAF, under grant #F336159411525 and ARPA order no. B550, National Science Foundation with grants MIP9225097, MIPS9625558, and CDA9623632, a Wisconsin Ro
- Appears in the proceedings of the 30th Annual International Symposium on Computer Architecture (ISCA-30)
- The Wisconsin Wind Tunnel Project: An Annotated Bibliography
- To appear in the Proceedings of the 25th Annual International Symposium on Computer Architecture (ISCA), 1998 Using Prediction to Accelerate Coherence Protocols
- A System-Level Specification Framework for I/O Architectures* Mark D. Hill, Anne E. Condon, Manoj Plakal, Daniel J. Sorin
- Cooperative Shared Memory: Software and Hardware for Scalable Multiprocessors
- Cache Performance of the Integer SPEC Benchmarks on a RISC Dionisios N. Pnevmatikatos
- WisconsinMadison {condon,markhill,plakal,sorin}@cs.wisc.edu Directorate,
- Optimistic Simulation of Parallel Architectures Using Program Executables \Lambda
- Parallel Computer Research in the Wisconsin Wind Tunnel Project Mark D. Hill, James R. Larus, and David A. Wood
- A Case for Deconstructing Hardware Transactional Memory Systems Mark D. Hill, Derek Hower, Kevin E. Moore,
- This work is supported in part by the National Science Foundation with grants MIP-9225097, MIPS-9625558, CCR 9257241, and CDA-9623632,
- Timestamp Snooping: An Approach for Extending SMPs
- 92 COmmuniCatiOns Of the aCm | jUNE 2009 | vOl. 52 | NO. 6 ParallEl ProGrammInG has long been
- A Comparison of Trace-Sampling Techniques for Multi-Megabyte Caches R. E. Kessler, Mark D. Hill, and David A. Wood
- SystemLevel Specification
- 0018-9162/03/$17.00 2003 IEEE50 Computer Simulating a $2M
- A "Flight Data Recorder" for Enabling Full-system Multiprocessor
- A Serializability Violation Detector for Shared-Memory Server Programs
- This work is supported in part by Wright Laboratory Avionics Director ate, Air Force Material Command, USAF, under grant #F33615941
- Appears in: ``Proceedings of the 1993 ACM SIGMETRICS Conference,'' May 1993. Reprinted by permission of ACM.
- Performance Implications of Tolerating Cache Faults Andreas Farid Pour
- Experimental Evaluation of On-Chip Microprocessor Cache Memories Mark D. Hill
- Lamport Clocks: Verifying A Directory Cache-Coherence Protocol (c) 1998 Plakal, Sorin, Condon, Hill
- This work is supported in part by the National Science Founda-tion, with grants EIA-9971256, CDA-9623632, and CCR-
- Efficient Support for Irregular Applications on DistributedMemory Machines \Lambda
- Multicast Snooping: A New Coherence Method Using A Multicast Address Multicast Snooping
- In late 2005, ACM President David Patterson charged the Health of Conferences Committee
- Appears in the Conf on Parallel Architectures and Compilation Techniques (PACT), Sep 2009 Abstract--Software testing is hard. The emergence of
- Bidirectional Technology Transfer: Sabbaticals in Industry
- Cache Performance of the SPEC92 Benchmark Suite Jeffrey D. Gee
- Fast Checkpoint/Recovery to Support KiloInstruction Speculation and Hardware Fault Tolerance
- Lamport Clocks: Verifying a Directory Cache-Coherence Protocol Manoj Plakal, Daniel J. Sorin, Anne E. Condon, Mark D. Hill
- Implementing Signatures for Transactional Memory Daniel Sanchez, Luke Yen, Mark D. Hill, Karthikeyan Sankaralingam
- Appears in: Proceedings of the 20th Annual International Symposium on Computer Architecture, May 1993. Mechanisms for Cooperative Shared Memory \Lambda
- To appear in the proceedings of ``ACM SIGMETRICS Conference on Measurement and Modeling of Computer Systems'', May 1991.
- To Appear in the Proceedings of the 18th Annual International Symposium on Computer Architecture Detecting Data Races on Weak Memory Systems +
- To appear in the Journal of Parallel and Distributed Systems, 1992 Programming for Different Memory Consistency Models **
- 0018-9162/98/$10.00 1998 IEEE42 Computer ith the advent of distributed computing
- RACE RECORDING FOR MULTITHREADED DETERMINISTIC REPLAY USING MULTIPROCESSOR HARDWARE
- The gem5 Simulator Nathan Binkert1
- ASPLOS-VII, Cambridge, MA, October 2-4, 1996 Synchronization and Communication
- Architecture-Conscious Database Systems
- Technical Report 1524, Computer Sciences Dept., UW-Madison, March 31, 2005 Thread-Level Transactional Memory
- Appears in: ``Supercomputing '94,'' Nov. 1994. Reprinted by permission of IEEE. ApplicationSpecific Protocols for UserLevel Shared Memory \Lambda
- Appears in the proceedings of the 13th Annual International Symposium on High Performance Computer Architecture (HPCA-13)
- To appear: Proceedings of the 8th ACM International Conference on Supercomputing, July 1994. An Evaluation of Directory Protocols for MediumScale
- To appear in the Nineteenth International Symposium on Computer Architecture, June 1992. Tradeoffs in Supporting Two Page Sizes **
- Permission to make digital or hard copies of all or part of this work for per-sonal or classroom use is granted without fee provided that copies are not
- CacheCoherence CacheCoherence
- Designing Memory Consistency Models For Shared-Memory Multiprocessors
- What is Scalability? 1 Mark D. Hill
- Facile: A Language and Compiler For High-Performance Processor Simulators1
- *Work done while at UW-Madison. Karma: Scalable Deterministic Record-Replay
- locality, in which contemporaneous references to a memory word come
- Appears in the proceedings of the 12th Annual International Symposium on High Performance Computer Architecture (HPCA-12)
- Permission to make digital or hard copies of all or part of this work for per-sonal or classroom use is granted without fee provided that copies are not
- This work is supported in part by the National Science Foundation (NSF), with grants CCF-0085949, CCR-0105721, EIA/CNS-0205286, CCR-0324878, as well as dona-
- Preliminary Draft A Primer on
- Calvin: Deterministic or Not? Free Will to Choose Derek R. Hower, Polina Dudnik, Mark D. Hill, and David A. Wood
- Supervised Memory systems use out-of-band met-abits to control and monitor accesses to normal data
- Karma: Scalable Deterministic Record-Replay Arkaprava Basu
- Opportunities Beyond Single-Core Microprocessors
- This work is supported in part by the U.S. National Science Foundation with grants EIA/CNS-0205286, CCR-0324878, CNS-0551401, and CNS-0720565, as well as
- OS Support for Virtualizing Hardware Transactional Memory
- This work is supported in part by the National Science Foundation (NSF), with grants EIA/CNS-0205286, CCR-0324878, and CNS-0551401, as well as donations from
- 2006 Mulitfacet Project University of Wisconsin-Madison Log-Based Transactional Memory
- 0018-9162/03/$17.00 2003 IEEE30 Computer in Computer
- 0018-9162/00/$10.00 2000 IEEE December 2000 67 R E S E A R C H F E A T U R E
- This work is supported in part by the National Science Foundation with grants MIP-9625558, EIA-9971256, and CDA-9623632, two Wisconsin
- A System-Level Specification Framework for I/O Architectures Mark D. Hill, Anne E. Condon, Manoj Plakal, Daniel J. Sorin
- A System-Level Specification Framework for I/O Architectures (c) 1999 Hill, Condon, Plakal, Sorin
- 0018-9162/98/$10.00 1998 IEEE70 Computer barrier to delivering improvements in net-
- This work is supported in part by Wright Laboratory Avionics Directorate, Air Force Material Command, USAF, under grant #F33615-94-1-1525 and ARPA order no. B550, National Science Foundation with grants MIP-9225097, MIPS-9625558, and CDA-9623632, a Wiscon
- The author argues that multiprocessors should support sequential consistency because--with speculative
- To appear in the Proceedings of the 25th Annual International Symposium on Computer Architecture (ISCA), 1998 Using Prediction to Accelerate Coherence Protocols
- Address Translation Mechanisms in Network Interfaces Ioannis Schoinas and Mark D. Hill
- June 8, 1993 Architectural
- Computer Sciences Technical Report #1051, September 1991, Revised September 1992 A Unified Formalization of Four Shared-Memory Models
- To appear in the Nineteenth International Symposium on Computer Architecture, June 1992. Tradeoffs in Supporting Two Page Sizes
- Implementing Stack Simulation for Highly-Associative Memories Yul H. Kim, Mark D. Hill, David A. Wood
- To appear in the Proceedings of the 1990 International Conference on Parallel Processing Implementing Sequential Consistency In Cache-Based Systems
- AN IN-CACHE ADDRESS TRANSLATION MECHANISM David A. Wood, Susan J. Eggers, Garth Gibson, Mark D. Hill, Joan M. Pendleton,
- HARDWARE SUPPORT FOR EFFICIENT TRANSACTIONAL AND SUPERVISED MEMORY SYSTEMS
- Designing Memory Consistency Models for Shared-Memory Multiprocessors
- Fine-Grain Distributed Shared Memory on Clusters of Workstations
- ARCHITECTURE-CONSCIOUS DATABASE SYSTEMS
- SIGNATURES IN TRANSACTIONAL MEMORY SYSTEMS A dissertation submitted in partial fulfillment of
- Now at VMware. Permission to make digital or hard copies of all or part of this work for personal or
- Evaluating a $2M Commercial Server on a $2K PC and Related Challenges
- Weak Ordering -A New Definition Sarita V. Adve
- In summary, the key to our work was (1) we took a more programmer-centric view of the problem com-
- Appears in the International Symposium on Computer Architecture (ISCA), June 2008 Current hardware transactional memory sys-
- Cache-Conscious Structure Layout Trishul M. Chilimbi Mark D. Hill
- This work is supported in part by the National Science Foundation, with grants EIA-9971256, CDA-9623632, and CCR-0105721, Intel Graduate
- Evaluating Non-deterministic Multi-threaded Commercial Workloads Alaa R. Alameldeen, Carl J. Mauer, Min Xu, Pacia J. Harper, Milo M.K. Martin, Daniel J. Sorin,
- Address Translation Mechanisms in Network Interfaces Ioannis Schoinas and Mark D. Hill
- DAP Spr.`98 UCB 1 Lecture 20
- APPLYING PROGRAMMING LANGUAGE IMPLEMENTATION
- (C) 2003 Milo Martin Token Coherence
- !#"!$%&')(0213547698 @)A!BC8EDF HG0A!6I@P6QR%1S5!"!TUP8VU(XW!Y# $`8V#$%5ab'c1d6eUYW57@)f#(XY (hg%i8V5fVpqUqrpRs
- Many commercial microprocessor architectures have added translation lookaside buffer (TLB) support for super-
- CACHE COHERENCE TECHNIQUES FOR MULTICORE PROCESSORS Michael R. Marty
- SINGLE-THREADED VS. MULTITHREADED: WHERE SHOULD
- To appear in the Journal of Parallel and Distributed Systems, 1992 Programming for Different Memory Consistency Models
- Design and Evaluation of Network Interfaces for System Area Networks
- Using Lamport Clocks to Reason About Relaxed Memory Models (c) 1999 Condon, Hill, Plakal, Sorin
- Page Placement Algorithms for Large Real-Indexed Caches R. E. Kessler
- Program Chair's Message Thank you for the privilege and burden of being the Program Committee Chair for the 2005
- MulticastSnooping:ANewCoherenceMethodUsingAMulticastAddress MulticastSnooping
- Appears in the proceedings of the 34th Annual ACM/IEEE International Symposium on Microarchitecture,
- http://www.cs.wisc.edu/multifacet Acknowledge
- Year of Introduction Intel iPSC/2
- Solving Microstructure Electrostatics on a Proposed Parallel Computer \Lambda
- Relaxed Consistency and Coherence Granularity in DSM Systems: A Performance Evaluation
- DBMSs On A Modern Processor: Where Does Time Go? Anastassia Ailamaki David J. DeWitt Mark D. Hill David A. Wood
- Appears in the proceedings of the 11th Annual International Symposium on High Performance Computer Architecture (HPCA-11), 2005
- Appears in the International Symposium on Computer Architecture (ISCA), June 2008 Multiprocessor deterministic replay has many
- A SystemLevel Specification Framework for I/O Architectures* Mark D. Hill, Anne E. Condon, Manoj Plakal, Daniel J. Sorin
- The Impact of Data Transfer and Buffering Alternatives on Network Interface Design Shubhendu S. Mukherjee and Mark D. Hill
- Many commercial microprocessor architectures have added translation lookaside buffer (TLB) support for super
- The Impact of Data Transfer and Buffering Alternatives on Network Interface Design Shubhendu S. Mukherjee and Mark D. Hill
- Cache Performance for Selected SPEC CPU2000 Benchmarks Version 1.0
- We aim to improve reliability of multithreaded programs by pro-posing a dynamic detector that detects potentially erroneous pro-
- Readings in Computer Architecture Mark D. Hill, University of Wisconsin-Madison Computer Sciences,
- To appear in the Proceedings of the 18th Annual International Symposium on Computer Architecture Comparison of Hardware and Software Cache Coherence Schemes
- A Comparison of TraceSampling Techniques for MultiMegabyte Caches 1 R. E. Kessler, Mark D. Hill, and David A. Wood
- Page Placement Algorithms for Large Real-Indexed Caches
- Debuggers have been proven indispensable in improv-ing software reliability. Unfortunately, on most real-life
- 12 1092-3063/00/$10.00 2000 IEEE IEEE Concurrency Wisconsin Wind Tunnel II
- We apply Amdahl's Law to multicore chips using symmet-ric cores, asymmetric cores, and dynamic techniques that
- 4/15/99 DRAFT: Readings in Computer Architecture 1 Morgan Kaufmann is pleased to present material from a preliminary draft of Readings in Computer Architecture;
- Parallel Computer Research in the Wisconsin Wind Tunnel Project Mark D. Hill, James R. Larus, and David A. Wood
- 2007 Multifacet Project University of Wisconsin-Madison Decoupling Hardware Transactional
- Destination-Set Prediction ISCA'03 -Milo Martinslide 2 Broadcast snooping
- Appears in the proceedings of the 8th Annual International Symposium on High-Performance Computer Architecture (HPCA-8)
- (C) 2001 Daniel Sorin Correctly Implementing Value Prediction
- Evaluating Non-deterministic Multi-threaded Commercial
- TOKEN COHERENCE Milo M. K. Martin
- Presidential Young Investigator Award: Cache Memory Design (MIPS-8957278)
- Using Criticality to Attack Performance Bottlenecks Brian Allen Fields
- (C) 2002 Milo Martin HPCA, Feb. 2002 Bandwidth Adaptive Snooping
- Why On-Chip Cache Coherence is Here to Stay Duke University Department of ECE Technical Report TR-2011-1
- The gem5 Simulator Brad Beckmann1
- EFFICIENTLY ENABLING CONVENTIONAL BLOCK
- Efficiently Enabling Conventional Block Sizes for Very Large Die-stacked DRAM Caches
