
- A 12-bit 80-Msample/s Pipelined ADC with Bootstrapped Digital Calibration
- A SecondOrder DoubleSampled DeltaSigma Modulator Using AdditiveError Switching +
- A Programmable Impedance Matching Circuit for Voiceband Modems
- Bandwidth Mismatch Correction for a Two-Channel Time-Interleaved A/D Converter
- Effect of Nonlinearity in the CMFB Circuit that Uses the Differential-Difference Amplifier*
- A 200 MS/s Passive Switched-Capacitor FIR Equalizer using a Time-Interleaved Topology*
- MODELING MEMORY ERRORS IN PIPELINED ANALOG-TO-DIGITAL John P. Keane, Paul J. Hurst, and Stephen H. Lewis
- *Research supported by UC MICRO grants 99-111 and 98-148. An Adaptive Analog Noise-Predictive Decision-Feedback Equalizer*
- Convergence Analysis of a Background Interstage Gain Calibration Technique for Pipelined ADCs*
- 3/27/2006 >REPLACE WITH YOUR PAPER IDENTIFICATION NUMBER (DOUBLE-CLICK HERE TO EDIT)< 1 Abstract--The sample-and-hold amplifier (SHA) in each
- Multirate Filter Bank Reconstruction of Signals from Bunched Samples
- An Adaptive DFE using an IIR Feedback Equalizer for 100BASE-TX Ethernet*
- Calibration of Sample-Time Error in a Two-Channel Time-Interleaved
- A Fully Differential Comparator Using a SwitchedCapacitor Differencing Circuit with CommonMode Rejection+
- Analog Timing Recovery for a Noise-Predictive DFE John P. Keane
- JSSC paper Last Modified: April 8, 1996 4:24 pm A 35Mb/s MixedSignal DecisionFeedback
- An 80Mb/s Adaptive DFE Detector in 1m CMOS * Session: 19.6
- An Adaptive Analog Noise-Predictive Decision-Feedback Equalizer * Michael Q. Le, Paul J. Hurst, John P. Keane
- * Research supported by UC MICRO grants 96077 and 97171. An Analog DFE for Disk Drives Using a MixedSignal Integrator *
- Two background calibration methods for timeinter leaved pipelined analogtodigital converters are described
- Dyer, Fu, Lewis, and Hurst 1 An Analog Background Calibration Technique for
- Copyright IEEE 2007. Personal use of this material is permitted. However, permission to use this material for any other purposes must be obtained from the IEEE by sending an email to pubs-permissions@ieee.org.
- A COMPARISON OF NOISESHAPING CLOCK GENERATORS FOR SWITCHEDCAPACITOR FILTERS *
- Analog Timing Recovery for a Noise-Predictive DFE
- A 12b DigitalBackgroundCalibrated Algorithmic ADC with 90 dB THD
- A Digital Background Calibration Technique for TimeInterleaved AnalogtoDigital Converters+
- Digital Background Calibration of an Algorithmic Analog-to-Digital Converter
- A 12-bit 20-Msample/s Pipelined Analog-to-Digital Converter with
- TIME-INTERLEAVED ANALOG-TO-DIGITAL CONVERTERS FOR DIGITAL COMMUNICATIONS
- A SecondOrder DoubleSampled DeltaSigma Modulator using IndividualLevel Averaging +
- A 12b 80MS/s Pipelined ADC with Bootstrapped Digital Calibration*
- A Full-Wave Rectifier for Interfacing with Multi-Phase Piezoelectric Energy Harvesters*
- A MixedSignal DecisionFeedback Equalizer That Uses Parallelism
- A CMOS Adaptive ContinuousTime Forward Equalizer, LPF and and RAMDFE for Magnetic Recording +
- CMOS CIRCUITS FOR THERMAL ASPERITY DETECTION AND RECOVERY IN DISK-DRIVE READ CHANNELS *
- JSSC Roo, Spencer, and Hurst A CMOS Analog Timing Recovery Circuit
- A 12-bit 20-MS/s Pipelined ADC with Nested Digital Background Calibration* X. Wang, P. J. Hurst, and S. H. Lewis
- *Research supported by UC MICRO Grants 96-077 and 97-171. An Analog DFE for Disk Drives Using a Mixed-Signal Integrator*
- * Research supported by UC MICRO Grant 98148. An Adaptive NoisePredictive DecisionFeedback Equalizer
- An 8-bit 13-Msamples/s Digital-Background-Calibrated Algorithmic ADC1 Eric B. Blecker, Ozan E. Erdogan2, Paul J. Hurst, and Stephen H. Lewis
- A Mixed-Signal Tuning Approach for Continuous-Time LPFs* Anthony Tong and Paul J. Hurst
- Timing Recovery for the Magnetic Recording Channel Using the Wave Difference Method