- To appear in Proceedings of the 24th International Symposium on Computer Architecture (ISCA), June, 1997 This paper introduces the concept of dynamic instruction reuse.
- Compiling for the Multiscalar Architecture T. N. Vijaykumar
- A CHARACTERIZATION OF PROLOG EXECUTION MARK ANDREW FRIEDMAN
- Memory Dependence Prediction Andreas Ioannis Moshovos
- To appear in the 31st International Symposium on Microarchitecture, Dec. 1998 Task Selection for a Multiscalar Processor
- THE MULTISCALAR ARCHITECTURE MANOJ FRANKLIN
- MEMORY SYSTEM DESIGN FOR BUS BASED MULTIPROCESSORS
- MASTER/SLAVE SPECULATIVE PARALLELIZATION AND APPROXIMATE CODE
- Incorporating Guarded Execution into Existing Instruction Sets Dionisios N. Pnevmatikatos
- Parallelism in the Front-End Paramjit S. Oberoi and Gurindar S. Sohi
- PRE-EXECUTION VIA SPECULATIVE DATA-DRIVEN MULTITHREADING A dissertation submitted in partial fulfillment
- Speculative Versioning Cache Sridhar Gopal
- Optimizing InterInstruction Value Communication through Degree of Use Prediction Jeffrey Adam Butts
- OVER-PROVISIONED MULTICORE SYSTEMS Koushik Chakraborty
- Recently two hardware techniques --Value Prediction (VP) and Instruction Reuse (IR) --have been proposed for exploiting the
- PREEXECUTION VIA SPECULATIVE DATADRIVEN MULTITHREADING A dissertation submitted in partial fulfillment
- Computing With Billion Transistor Chips Computer Sciences Department
- DESIGN AND EVALUATION OF A MULTISCALAR PROCESSOR
- To appear in ASPLOS `98 We study the phenomenon of instruction repetition, where the inputs
- Mixed-Mode Multicore Reliability Philip M. Wells
- Serialization Sets: A Dynamic Dependence-Based Parallel Execution Model
- Computation Spreading: Employing Hardware Migration to Specialize CMP Cores On-the-fly
- Hardware Support for Spin Management in Overcommitted Virtual Machines
- Program Demultiplexing: Data-flow based Speculative Parallelization of Methods in Sequential Programs
- Cooperative Caching for Chip Multiprocessors Jichuan Chang and Gurindar S. Sohi
- Multiprocessing and multithreading are becoming ubiquitous even on single chips.
- Exploiting Value Locality in Physical Register Files Saisanthosh Balakrishnan Gurindar S. Sohi
- Out-of-Order Instruction Fetch using Multiple Sequencers Paramjit Oberoi and Gurindar Sohi
- Speculative Multithreaded Processors Gurindar S. Sohi and Amir Roth
- Current techniques for prefetching linked data structures (LDS) exploit the work available in one loop iteration or
- We revisit memory hierarchy design viewing memory as an inter-operation communication agent. This perspective leads to
- High-Bandwidth Address Translation for Multiple-Issue Processors
- Appendix: Detailed Results This document includes the detailed results for the paper "High-Bandwidth Address Translation for Multiple-Issue Processors", by Todd
- ARB: A Hardware Mechanism for Dynamic Reordering of Memory References* Manoj Franklin Gurindar S. Sohi
- Zero-Cycle Loads: Microarchitecture Support for Reducing Load Latency
- Streamlining Data Cache Access with Fast Address Calculation
- Request Combining in Multiprocessors with Arbitrary Interconnection Networks Alvin R. Lebeck and Gurindar S. Sohi
- Guarded Execution and Branch Prediction in Dynamic ILP Processors Dionisios N. Pnevmatikatos Gurindar S. Sohi
- THE EXPANDABLE SPLIT WINDOW PARADIGM FOR EXPLOITING FINE-GRAIN PARALLELISM
- PROGRAM DEMULTIPLEXING: DATA-FLOW BASED SPECULATIVE PARALLELIZATION OF METHODS IN SEQUENTIAL PROGRAMS
- Optimizing Inter-Instruction Value Communication through Degree of Use Prediction Jeffrey Adam Butts
- # $&%'() 0)12%'33!) Scott Elliott Breach
- Compiling for the Multiscalar Architecture T. N. Vijaykumar
- Incorporating Guarded Execution into Existing Instruction Sets Dionisios N. Pnevmatikatos
- A CHARACTERIZATION OF PROLOG EXECUTION MARK ANDREW FRIEDMAN
- MEMORY SYSTEM DESIGN FOR BUS BASED MULTIPROCESSORS
- Appears in Computer Architecture News (CAN), September 2005 The Wisconsin Multifacet Project has created a sim-
- FYI: The Title Page, Abstract, Acknowledgements, Table of Contents, List of Tables, and List of Figures are printed after the Chapters and the References.
- DATA-DRIVEN DECOMPOSITION OF SEQUENTIAL PROGRAMS FOR DETERMINATE PARALLEL EXECUTION
- Use-Based Register Caching with Decoupled Indexing J. Adam Butts and Gurindar S. Sohi
- Serializing Instructions in System-Intensive Workloads: Amdahl's Law Strikes Again
- Dynamic Dead-Instruction Detection and Elimination J. Adam Butts and Guri Sohi
- MASTER/SLAVE SPECULATIVE PARALLELIZATION AND APPROXIMATE CODE
- Appearing in the 28th Annual International Symposium on Computer Architecture (ISCA 2001), July, 2001. A relatively small set of static instructions has significant
- Appears in the proceedings of the 35th International Symposium on Microarchitecture (Micro-35), November 20-22, 2002 Craig Zilles
- To appear at the Seventh International Symposium on High Performance Computer Architecture (HPCA-7), January 19-24, 2001 Aggressive program optimization requires accurate profile
- Appears in the Proceedings of Micro-32 Computer Sciences Department, University of Wisconsin -Madison
- DYNAMIC INSTRUCTION REUSE AVINASH SODANI
- HARDWARE AND SOFTWARE MECHANISMS FOR REDUCING LOAD LATENCY
- Coherence Decoupling: Making Use of Incoherence Jaehyuk Huh
- Appears in the Proceedings of the 24th Annual International Symposium on Computer Architecture Data dependence speculation is used in instruction-level
- Multiscalar Processors Gurindar S. Sohi Scott E. Breach T.N. Vijaykumar
- Speculative Versioning Cache Sridhar Gopal, T. N. Vijaykumar, James E. Smith and Gurindar S. Sohi
- A Static Power Model for Architects J. Adam Butts and Gurindar S. Sohi
- ADAPTING TO DYNAMIC HETEROGENEITY: VIRTUALIZATION FOR THE MULTICORE ERA
- Control Flow Prediction For Dynamic ILP Processors Dionisios N. Pnevmatikatos Manoj Franklin Gurindar S. Sohi
- THE MULTISCALAR ARCHITECTURE MANOJ FRANKLIN
- DYNAMIC INSTRUCTION REUSE AVINASH SODANI
- Cooperative Cache Partitioning for Chip Multiprocessors Jichuan Chang and Gurindar S. Sohi
- Proc. 25th Annual International Symposium on Microarchitecture (MICRO-25), 1992 Register Traffic Analysis for Streamlining Inter-Operation Communication
- Microprocessors --10 Years Back, 10 Years Gurindar S. Sohi
- Guarded Execution and Branch Prediction in Dynamic ILP Processors Dionisios N. Pnevmatikatos and Gurindar S. Sohi
- FYI: The Title Page, Abstract, Acknowledgements, Table of Contents, List of Tables, and List of Figures are printed after the Chapters and the References.
- Cooperative Caching for Chip Multiprocessors Jichuan Chang
- Appears in the Proceedings of the 27th Annual International Symposium on Computer Architecture (ISCA-2000), June 12-14, 2000. For many applications, branch mispredictions and cache misses
- Characterizing and Predicting Value Degree of Use J. Adam Butts and Gurindar S. Sohi
- Dataflow Execution of Sequential Imperative Programs on Multicore Architectures
