- Circuits for High-Performance Low-Power VLSI Logic Submitted to the Department of Electrical Engineering and Computer Science
- SCALE DRAM Subsystem Power Analysis Vimal Bhalodia
- Globally Synchronized Frames for Guaranteed Quality-of-Service in Shared Memory Systems
- Parameterized DRAM Model by Yong-jin Kwon
- Virtualizing Local Stores by Henry M. Cook
- Re-Architecting DRAM Memory Systems with Monolithically Integrated Silicon Photonics
- Active Row Precharge Activate
- Summarizing Multiprocessor Program Execution with Versatile, Microarchitecture-Independent Snapshots
- Energy Aware Lossless Data Compression Kenneth C. Barr
- Appears in Workshop on Complexity-Effective Design, 28th ISCA, Gothenburg, Sweden, June 2001 1 The Span Cache: Software Controlled Tag Checks and Cache Line Size
- INTERNATIONAL COMPUTER SCIENCE INSTITUTE I1947 Center St. Suite 600 Berkeley, California 94704-1198 510 643-9153 FAX 510 643-7684
- Designing Multisocket Systems with Silicon Photonics by Scott Beamer
- ZOOM: A Performance-Energy Cache Simulator S.B. Electrical Engineering and Computer Science, June 2002
- Resource Management in the Tessellation Manycore OS Juan A. Colmenares, Sarah Bird, Henry Cook, Paul Pearce, David Zhu, John Shalf
- Appears in Workshop on Memory Access Decoupled Architectures, PACT-01, Barcelona, Spain, September 2001 1 Multithreading Decoupled Architectures for Complexity-Effective
- Designing Multi-socket Systems Using Silicon Photonics Scott Beamer, Krste Asanovic
- Computer Science and Artificial Intelligence Laboratory Victim Migration: Dynamically Adapting Between
- The Landscape of Parallel Computing Research: A View from Berkeley
- 56 CommuniCAtions of the ACm | oCtobER 2009 | vol. 52 | No. 10 contributed articles
- The RISC-V Instruction Set Manual, Volume I: Base User-Level ISA
- Vector-Thread Architecture And Implementation Ronny Meir Krashinsky
- RAMP Gold: An FPGA-based Architecture Simulator for Multiprocessors
- Conditional Move Shift Right
- The T0 Vector Microprocessor Krste Asanovic
- Banked Microarchitectures for Complexity-Effective Superscalar Microprocessors
- Datacenter-Scale Network Research on FPGAs Zhangxi Tan
- An FPGA-based Simulator for Datacenter Networks Zhangxi Tan
- L2 Cache to Off-chip Memory Networks for Chip Multiprocessors by Carrell D Killebrew
- Appears in IEEE International High Level Design Validation and Test Workshop, November 2007 Transactors for Parallel Hardware and Software Co-Design
- Research Accelerator for Multiple Processors
- MIT CSAIL Technical Report (MIT-LCS-TR-957), July 2004 1 Dynamically Resizable Static CMOS Logic for Fine-Grain Leakage Reduction
- Programmable Neurocomputing Krste Asanovic
- Fine-Grain CAM-Tag Cache Resizing Using Miss Tags Michael Zhang
- Exposing Datapath Elements to Reduce Microprocessor Energy Consumption
- Custom made Sponge Paint primitives
- INTERNATIONAL COMPUTER SCIENCE INSTITUTE I1947 Center St. Suite 600 Berkeley, California 94704-1198 510 643-9153 FAX 510 643-7684
- ()012 30456789@A B4C20 D2@EA D2)1)45F G)8006HA D)845 IP QP (85R0SH)TA U B6V5 W4X)YT52E
- 394 IEEE TRANSACTIONS ON NEURAL NETWORKS, VOL. 4, NO. 3, MAY 1993 The Design of a Neuro-Microprocessor
- The Parallel Computing Laboratory at U.C. Berkeley: A Research Agenda Based on the Berkeley View
- A Case for FAME: FPGA Architecture Model Execution Zhangxi Tan, Andrew Waterman, Henry Cook, Sarah Bird, Krste Asanovic, David Patterson
- Cooperative Hierarchical Resource Management for Efficient Composition of Parallel Software
- Simplified Vector-Thread Architectures for Flexible and Efficient Data-Parallel Accelerators
- Software Knows Best: A Case for Hardware Transparency and Measurability
- Emulation of Microprocessor Memory Systems Using the RAMP Design Framework
- In 25th IEEE International Conference on Computer Design (ICCD-2007), Lake Tahoe, CA, October 2007. Continual Hashing for Efficient Fine-grain State Inconsistency Detection
- Mondriaan Memory Protection Emmett Jethro Witchel
- Appears in: The 29th Annual Int'l Symposium for Computer Architecture (ISCA-29), Anchorage, AK, May 2002 Dynamic Fine-Grain Leakage Reduction Using Leakage-Biased Bitlines
- Reducing Instruction Cache Energy Using Gated Wordlines Mukaya Panich
- Optimizing Matrix Multiply using PHiPAC: a Portable, High-Performance, ANSI C Coding Methodology
- A Supercomputer for Neural Computation Krste Asanovi c, James Beck, Jerome Feldman, Nelson Morgan, and John Wawrzynek
- CNS-1 Architecture Specification A Connectionist Network Supercomputer
- Evaluation of a Stall" Cache: An E cient Restricted On-chip Instruction Cache
- Spoken Natural Language Understanding as a Parallel Application K. Asanovic, J. R. Chapman
- VISTA: A Visualization Tool for Computer Architects Aaron D. Mihalik
- High Performance, Variable-Length Instruction Encodings Submitted to the Department of Electrical Engineering and Computer
- The RAMP Architecture & Description Language Greg Gibeling, Andrew Schultz & Krste Asanovic
- The Extreme Benchmark Suite: Measuring High-Performance Embedded Systems
- Mondrian Memory Protection Emmett Witchel, Josh Cates, and Krste Asanovic
- Appears in IEEE Workshop on VLSI, Orlando, Florida, April 2001 Load-Sensitive Flip-Flop Characterization
- Reducing Exception Management Overhead with Software Restart Markers
- PARALLEL NEURAL NETWORK TRAINING ON MULTI-SPERT
- Composing Parallel Software Efficiently with Lithe Massachusetts Institute of Technology
- A Double-Pulsed Set-Conditional-Reset Flip-Flop Albert Ma and Krste Asanovic
- Design-Space Exploration for CMOS Photonic Processor Vladimir Stojanovia
- SPACE: SYMBOLIC PROCESSING IN ASSOCIATIVE COMPUTING ELEMENTS
- Vector Microprocessors Krste Asanovic
- Rethinking Hardware Support for Network Analysis and Intrusion Prevention
- Computer Science and Artificial Intelligence Laboratory Technical Report
- LAPACK Working Note 111, UTK, http://www.netlib.org/lapack/lawns Optimizing Matrix Multiply using PHiPAC: a Portable,
- Optimal Digital System Design in Deep Submicron Technology Seongmoo Heo
- Torrent Architecture Manual Krste Asanovi c
- T0: A SingleChip Vector Microprocessor with Reconfigurable Pipelines
- M U LTI CORE COMPUTING Rumors of the death of Moore's Law are greatly exaggerated, according to a
- Appears in: The 2002 Symposium on VLSI Circuits, Honolulu, HI, June 2002 Leakage-Biased Domino Circuits for Dynamic Fine-Grain Leakage Reduction
- Approved for Public Release, Distribution Unlimited. CEARCH: Cognition Enabled Architecture
- Building Manycore Processor-to-DRAM Networks with Monolithic Silicon Photonics
- Hardware Support for Unbounded Transactional Memory
- Energy-Efficient Register File Design Jessica Hui-Chun Tseng
- A Low-Power 32 bit Datapath Design Seongmoo Heo
- Technical Report UCB//CSD-05-1412, September 2005 RAMP: Research Accelerator for Multiple Processors -
- Low-Power Single-Precision IEEE Floating-Point Sheetal A. Jain
- Appears in 19th Conference on Advanced Research in VLSI, Salt Lake City, UT, March 2001 Activity-Sensitive Flip-Flop and Latch Selection
- Video over IP: An Example Reconfigurable Computing Application for a Handheld Device
- Versatility and VersaBench: A New Metric and a Benchmark Suite for Flexible Architectures
- Energy-Exposed Instruction Set Architectures Krste Asanovic
- RAMP Blue: Implementation of a Manycore 1008 Processor FPGA System D. Burke, J. Wawrzynek, K. Asanovi, A. Krasnov, A. Schultz, G. Gibeling, P.-Y. Droz
- Fast Fourier Transform on a 3D FPGA Elizabeth Basha
- A Speculative Control Scheme for an Energy-Efficient Banked Register File
- BUILDING MANY-CORE PROCESSOR-TO-DRAM NETWORKS
- Searching for a Parent Instead of Fighting Over Children: A Fast Breadth-First Search Implementation
- The Case for User-Level Preemptive Scheduling to Support Multi-Rate Audio Applications for Multi-Core Processors
