Cong, Jason "Jingsheng" - Computer Science Department, University of California at Los Angeles

• A New Enhanced SPFD Rewiring Algorithm Jason Cong*
• IEEE TRANSACTIONS ON COMPUTER-AIDED DESIGN OF INTEGRATED CIRCUITS AND SYSTEMS, VOL. 21, NO. 3, MARCH 2002 319 Wire Width Planning for Interconnect
• IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS, VOL. 9, NO. 6, DECEMBER 2001 929 Buffer Block Planning for Interconnect Planning and
• 550 IEEE TRANSACTIONS ON COMPUTER-AIDED DESIGN OF INTEGRATED CIRCUITS AND SYSTEMS, VOL. 23, NO. 4, APRIL 2004 Architecture and Synthesis for On-Chip
• Simultaneous Placement with Clustering and Duplication
• RASP: A General Logic Synthesis System for SRAM-based FPGAs Jason Cong and John Peck
• Architecture-Level Synthesis for Automatic Interconnect Pipelining
• An Improved Graph-Based FPGA Technology Mapping Algorithm For Delay Optimization
• mPL6: Enhanced Multilevel Mixed-Size Placement Tony F. Chan,
• Microarchitecture Evaluation With Physical Planning Jason Cong, Ashok Jagannathan, Glenn Reinman, Michail Romesis
• Performance Driven Multi-level and Multiwa yPartitioning with Retiming
• Behavior-Level Observability Don't-Cares and Application to Low-Power Behavioral Synthesis
• An Interconnect Energy Model Considering Coupling Effects Taku Uchino
• Exploiting Signal Flow and Logic Dependency in Standard Cell Placement
• A Multilevel Analytical Placement for 3D ICs Abstract -In this paper we propose a multilevel non-linear
• Multilevel Global Placement with Retiming Department of Computer Science
• Accelerating Sequential Applications on CMPs Using Core Spilling
• Bounded-Skew Clock and Steiner Routing JASON CONG, ANDREW B. KAHNG, CHENG-KOK KOH, and C.-W.
• ACMJ042-10 ACM-TRANSACTION April 1, 2005 20:5 Large-Scale Circuit Placement
• Improved SAT-Based Boolean Matching Using Implicants for LUT-Based FPGAs
• Partially-Dependent Functional Decomposition with Applications in FPGA Synthesis and Mapping
• Improved Crosstalk Modeling for Noise Constrained Interconnect Optimization Jason Cong, David Zhigang Pan and Prasanna V. Srinivas
• LUT-Based FPGA Technology Mapping under Arbitrary Net-Delay Models
• Synthesis of an Application-Specific Soft Multiprocessor Jason Cong, Guoling Han and Wei Jiang
• Energy Efficient Multiprocessor Task Scheduling under Input-dependent Variation Jason Cong and Karthik Gururaj
• Fine Grain 3D Integration for Microarchitecture Design Through Cube Packing Exploration*
• Thermal Via Planning for 3-D ICs Computer Science Department, UCLA
• An Enhanced Multilevel Routing System* Jason Cong, Min Xie, Yan Zhang
• Generating More Compactable Channel Routing Solutions1 Jingsheng Cong
• Analog Integrated Circuits and Signal Processing 5, 19-30 (1994) 1994 Kluwer Academic Publishers, Boston. Manufactured in The Netherlands.
• 410 IEEE TRANSACTIONS ON COMPUTER-AIDED DESIGN OF INTEGRATED CIRCUITS AND SYSTEMS, VOL. 16, NO. 4, APRIL 1997 [35] C. Sechen and K.-W. Lee, "An improved simulated annealing algorithm
• 24 IEEE TRANSACTIONS ON COMPUTER-AIDED DESIGN OF INTEGRATED CIRCUITS AND SYSTEMS, VOL. 17, NO. 1, JANUARY 1998 Efficient Algorithms for the Minimum
• 608 IEEE TRANSACTIONS ON COMPUTER-AIDED DESIGN OF INTEGRATED CIRCUITS AND SYSTEMS, VOL. 18, NO. 5, MAY 1999 An Efficient Approach to Multilayer Layer
• IEEE TRANSACTIONS ON COMPUTER-AIDED DESIGN OF INTEGRATED CIRCUITS AND SYSTEMS, VOL. 18, NO. 11, NOVEMBER 1999 1595 Optimal FPGA Mapping and Retiming
• IEEE TRANSACTIONS ON COMPUTER-AIDED DESIGN OF INTEGRATED CIRCUITS AND SYSTEMS, VOL. 19, NO. 2, FEBRUARY 2000 215 Via Design Rule Consideration in Multilayer Maze
• IEEE TRANSACTIONS ON COMPUTER-AIDED DESIGN OF INTEGRATED CIRCUITS AND SYSTEMS, VOL. 21, NO. 7, JULY 2002 763 An Interconnect Energy Model Considering
• 346 IEEE TRANSACTIONS ON COMPUTER-AIDED DESIGN OF INTEGRATED CIRCUITS AND SYSTEMS, VOL. 23, NO. 3, MARCH 2004 Edge Separability-Based Circuit Clustering With
• 382 IEEE TRANSACTIONS ON COMPUTER-AIDED DESIGN OF INTEGRATED CIRCUITS AND SYSTEMS, VOL. 24, NO. 3, MARCH 2005 MARS--A Multilevel Full-Chip
• IEEE TRANSACTIONS ON COMPUTER-AIDED DESIGN OF INTEGRATED CIRCUITS AND SYSTEMS, VOL. 25, NO. 9, SEPTEMBER 2006 1719 Fast Floorplanning by Look-Ahead Enabled
• IEEE TRANSACTIONS ON COMPUTER-AIDED DESIGN OF INTEGRATED CIRCUITS AND SYSTEMS, VOL. 25, NO. 12, DECEMBER 2006 2687 Protecting Combinational Logic Synthesis Solutions
• IEEE TRANSACTIONS ON COMPUTER-AIDED DESIGN OF INTEGRATED CIRCUITS AND SYSTEMS, VOL. 27, NO. 12, DECEMBER 2008 2133 Highly Efficient Gradient Computation for
• Investigating the Effects of Fine-Grain Three-Dimensional Integration
• Simultaneous Resource Binding and Interconnection Optimization Based on a
• 1318 IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS, VOL. 17, NO. 9, SEPTEMBER 2009 Synthesis Algorithm for Application-Specific
• FPGA-Based Hardware Acceleration of Lithographic Aerial Image Simulation
• IEEE TRANSACTIONS ON COMPUTER-AIDED DESIGN OF INTEGRATED CIRCUITS AND SYSTEMS, VOL. 29, NO. 11, NOVEMBER 2010 1709 Technology Mapping and Clustering for FPGA
• 1750 IEEE TRANSACTIONS ON COMPUTER-AIDED DESIGN OF INTEGRATED CIRCUITS AND SYSTEMS, VOL. 29, NO. 11, NOVEMBER 2010 Evaluating Statistical Power Optimization
• Automatic Memory Partitioning and Scheduling for Throughput and Power Optimization
• Customizable Domain-Specific Computing
• IEEE TRANSACTIONS ON COMPUTER-AIDED DESIGN OF INTEGRATED CIRCUITS AND SYSTEMS, VOL. 30, NO. 4, APRIL 2011 473 High-Level Synthesis for FPGAs: From
• A Fast Multilayer General Area Router for MCM Designs
• A Fast Four-Via Multilayer MCM Router Kei-Yong Khoo and Jason Cong
• AN OPTIMAL PERFORMANCE-DRIVEN TECHNOLOGY MAPPING ALGORITHM FOR LUT-BASED FPGAS UNDER ARBITRARY NET-DELAY MODELS
• Placement and Placement Driven Technology Mapping for FPGA Synthesis Tong Gao, Kuang-Chien Chen Jason Cong, Yuzheng Ding C. L. Liu
• Multi-Way VLSI Circuit Partitioning Based on Dual Net Representation Jason Cong, Wilburt Labio, and Narayanan Shivakumar
• Simultaneous Driver and Wire Sizing for Performance and Power Optimization
• Parallel Logic Level simulation of VLSI Circuits In this paper, we study parallel logic level simulation of combinational VLSI Boolean
• On Nominal Delay Minimization in LUT-Based FPGA Technology Mapping Jason Cong and Yuzheng Ding
• Bounded-Skew Clock and Steiner Routing Under Elmore Delay Jason Cong, Andrew B. Kahng, Cheng-Kok Koh and C.-W. Albert Tsao
• Simultaneous Buffer and Wire Sizing for Performance and Power Optimization Jason Cong, Cheng-Kok Koh Kwok-Shing Leung
• An E cient Approach to Multi-layer Layer Assignment with Application to Via Minimization 1
• Interconnect Design for Deep Submicron ICs , Lei He, Kei-Yong Khoo, Cheng-Kok Koh and Zhigang Pan
• 0-89791-993-9/97 $10.00 1997 IEEE Interconnect Layout Optimization Under Higher-Order RLC Model
• Boolean Matching for Complex PLBs in LUT-based FPGAs with Application to Architecture Evaluation
• INTELLECTUAL PROPERTY PROTECTION BY WATERMARKING COMBINATIONAL LOGIC SYNTHESIS SOLUTIONS
• Multiway Partitioning with Pairwise Movement Jason Cong and Sung Kyu Lim
• An Interconnect-Centric Design Flow for Nanometer Technologies Department of Computer Science
• An Implicit Connection Graph Maze Routing Algorithm for ECO Routing Jason Cong, Jie Fang and Kei-Yong Khoo
• Technology Mapping for k/m-macrocell Based FPGAs Jason Cong, Hui Huang, and Xin Yuan
• Theory and Algorithm for SPFD-Based Global Rewiring Jason Cong and Wangning Long
• Timing Closure Based on Physical Hierarchy Computer Science Department
• Optimality and Scalability Study of Existing Placement Algorithms Chin-Chih Chang1
• Placement-Driven Technology Mapping for LUT-Based FPGAs Joey Y. Lin*
• Optimality, Scalability and Stability Study of Partitioning and Placement Algorithms
• OPTIMALITY AND STABILITY STUDY OF TIMING-DRIVEN PLACEMENT Jason Cong, Michail Romesis, Min Xie
• Architectural Synthesis Integrated with Global Placement for Multi-Cycle Communication*
• Gradual Relaxation Techniques with Applications to Behavioral Synthesis*
• Large-Scale Circuit Placement: Gap and Promise Jason Cong, Tim Kong,
• Application-Specific Instruction Generation for Configurable Processor Architectures
• An Area-Optimality Study of Floorplanning Jason Cong, Gabriele Nataneli, Michail Romesis, and Joseph R. Shinnerl
• A Communication-Centric Approach To Instruction Steering For Future Clustered Processors
• Routability-Driven Placement and White Space Allocation Chen Li , Min Xie, Cheng-Kok Koh , Jason Cong, Patrick H. Madden
• Optimal Module and Voltage Assignment for Low-Power Deming Chen+
• Simultaneous Timing-Driven Placement and Duplication Magma Design Automation
• A Robust Detailed Placement for Mixed-Size IC Designs Jason Cong and Min Xie
• An Automated Design Flow for 3D Microarchitecture Evaluation* Jason Cong1
• PLATFORM-BASED BEHAVIOR-LEVEL AND SYSTEM-LEVEL SYNTHESIS
• Thermal-Aware Physical Design Flow for 3-D ICs Jason Cong and Yan Zhang
• Micro-architecture Pipelining Optimization with Throughput-Aware Floorplanning Yuchun Ma* Zhuoyuan Li* Jason Cong Xianlong Hong Glenn Reinman Sheqin Dong* Qiang Zhou
• 3D Architecture Modeling and Exploration Jason Cong,
• Behavioral Synthesis with Activating Unused Flip-Flops for Reducing Glitch Power in FPGA
• LP Based White Space Redistribution for Thermal Via Planning and Performance Optimization in 3D ICs*
• Lithographic Aerial Image Simulation with FPGA-Based Hardware Acceleration
• Robust Gate Sizing via Mean Excess Delay Minimization Jason Cong1,2
• Power Reduction of CMP Communication Networks via RF-Interconnects M-C. Frank Chang
• Evaluation of Static Analysis Techniques for Fixed-Point Precision Optimization
• FCUDA: Enabling Efficient Compilation of CUDA Kernels onto FPGAs*
• Abstract--3D IC technologies have recently attracted great attention due to the potential performance improvement, power
• A Variation-Tolerant Scheduler for Better Than Worst-Case Behavioral Synthesis
• A Scalable Micro Wireless Interconnect Structure for CMPs Suk-Bok Lee
• Scheduling with Soft Constraints cong@cs.ucla.edu
• Bit-Level Optimization for High-Level Synthesis and FPGA-Based Acceleration
• Coordinated Resource Optimization in Behavioral Synthesis Jason Cong Bin Liu Junjuan Xu
• An Analytical Placer for Mixed-Size 3D Placement Jason Cong,
• LUT-Based FPGA Technology Mapping for Reliability Jason Cong and Kirill Minkovich
• AXR-CMP: Architecture Support in Accelerator-Rich CMPs UCLA, CS Department
• 488 2011 IEEE International Solid-State Circuits Conference ISSCC 2011 / SESSION 28 / DRAM & HIGH-SPEED I/O / 28.1
• AN EFFICIENT APPROACH TO SIMULTANEOUS TRANSISTOR AND INTERCONNECT SIZING
• Microarchitecture Evaluation With Floorplanning And Interconnect Pipelining
• Enhanced SPFD Rewiring on Improving Rewiring Ability Jason Cong*
• Multiband RF-Interconnect for Reconfigurable Network-on-Chip Communications
• Acyclic Multi-Way Partitioning of Boolean Networks Jason Cong, Zheng Li, and Rajive Bagrodia
• MCM Layout with Distributed-RLC Model D. Zhou and F. Tsui
• RF Interconnects for Communications On-chip1 The authors would like to acknowledge the supports from DARPA and FCRP GSRC for this research.
• Bitwidth-Aware Scheduling and Binding in High-Level Synthesis
• SPFD-Based Global Rewiring Jason Cong, Yizhou Lin, Wangning Long*
• On Area/Depth Trade-off in LUT-Based FPGA Technology Mapping Jason Cong and Yuzheng Ding
• Relaxed Simulated Tempering for VLSI Floorplan Designs Jason Cong, Tianming Kong, Dongmin Xu
• Accelerating Monte Carlo based SSTA Using FPGA Jason Cong, Karthik Gururaj, Wei Jiang, Bin Liu, Kirill Minkovich, Bo Yuan and Yi Zou
• Lower-Bound Estimation for Multi-Bitwidth Scheduling Junjuan Xu*+
• Structural Gate Decomposition for Depth-Optimal Technology Mapping in LUT-
• Thermal-Aware 3D IC Placement Via Transformation Jason Cong, Guojie Luo, Jie Wei and Yan Zhang
• Bit-Level Transformation and Optimization for Hardware Synthesis of Algorithmic Descriptions
• 986 IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS, VOL. 14, NO. 9, SEPTEMBER 2006 Architecture and Compiler Optimizations for Data
• Minimum-Cost Bounded-Skew Clock Routing Jason Cong and Cheng-Kok Koh
• Behavior and Communication Co-Optimization for Systems with Sequential Communication Media
• IEEE TRANSACTIONS ON COMPUTER-AIDED DESIGN OF INTEGRATED CIRCUITS AND SYSTEMS, VOL. 20, NO. 9, SEPTEMBER 2001 1077 Boolean Matching for LUT-Based Logic Blocks
• ACES: Application-Specific Cycle Elimination and Splitting for Deadlock-Free Routing on Irregular Network-on-Chip
• IEEE TRANSACTIONS ON COMPUTER-AIDED DESIGN OF INTEGRATED CIRCUITS AND SYSTEMS, VOL. 20, NO. 5, MAY 2001 633 DUNE--A Multilayer Gridless Routing System
• A New Algorithm for Standard Cell Global Routing Department of Computer Science
• An Efficient Multilayer MCM Router Based on Four-Via Routing Kei-Yong Khoo and Jason Cong
• An Efficient and Versatile Scheduling Algorithm Based On SDC Formulation
• Parallel Multi-level Analytical Global Placement on Graphics Processing Units
• Architecture and Synthesis for Multi-Cycle Communication For multi-gigahertz designs in nanometer technologies, data
• Analysis and Justi cation of a Simple, Practical 2 1 2-D Capacitance Extraction Methodology
• A Comparative Study on the Architecture Templates for Dynamic Nested Loops Jason Cong and Yi Zou
• 598 IEEE TRANSACTIONS ON COMPUTER-AIDED DESIGN OF INTEGRATED CIRCUITS AND SYSTEMS, VOL. 20, NO. 5, MAY 2001 Pseudopin Assignment with Crosstalk Noise Control
• A Unified Optimization Framework for Simultaneous Gate Sizing and Placement under Density Constraints
• Simultaneous Depth and Area Minimization in LUT-based FPGA Mapping Jason Cong and Yean-Yow Hwang
• MC-Sim: An Efficient Simulation Tool for MPSoC Designs Jason Cong, Karthik Gururaj, Guoling Han, Adam Kaplan, Mishali Naik, Glenn Reinman
• Power Model for Interconnect Planning Chin-Chih Chang
• Performance-Driven Multi-Level Clustering with Application to Hierarchical FPGA Mapping
• 230 IEEE TRANSACTIONS ON COMPUTER-AIDED DESIGN OF INTEGRATED CIRCUITS AND SYSTEMS, VOL. 26, NO. 2, FEBRUARY 2007 Optimality Study of Logic Synthesis
• 1684 IEEE TRANSACTIONS ON COMPUTER-AIDED DESIGN OF INTEGRATED CIRCUITS AND SYSTEMS, VOL. 23, NO. 12, DECEMBER 2004 Retiming-Based Timing Analysis with an Application to
• A Rigorous Framework for Convergent Net Weighting Schemes in Timing-Driven Placement
• 858 IEEE TRANSACTIONS ON COMPUTER-AIDED DESIGN OF INTEGRATED CIRCUITS AND SYSTEMS, VOL. 26, NO. 5, MAY 2007 Routability-Driven Placement and
• IEEE TRANSACTIONS ON COMPUTER-AIDED DESIGN OF INTEGRATED CIRCUITS AND SYSTEMS, VOL. 20, NO. 12, DECEMBER 2001 1455 Short Papers_______________________________________________________________________________
• On the Futility of Statistical Power Optimization Jason Cong1,2
• Beyond the Combinatorial Limit in Depth Minimization for LUT-Based FPGA Designs
• Optimality Study of Logic Synthesis for LUT-Based FPGAs Jason Cong and Kirill Minkovich
• Robust Mixed-Size Placement Under Tight White-Space Constraints
• Global Clustering-Based Performance-Driven Circuit Partitioning
• Instruction Set Extension with Shadow Registers for Configurable Processors
• Behavior-Level Observability Analysis for Operation Gating in Low-Power
• Physical Hierarchy Generation with Routing Congestion Chin-Chih Chang
• A Generalized Control-Flow-Aware Pattern Recognition Algorithm for Behavioral Synthesis
• IEEE TRANSACTIONS ON COMPUTER-AIDED DESIGN OF INTEGRATED CIRCUITS AND SYSTEMS, VOL. 20, NO. 6, JUNE 2001 739 Interconnect Performance Estimation Models for
• Logic-on-Logic 3D Integration and Placement Thorlindur Thorolfsson, Guojie Luo, Jason Cong and Paul D. Franzon
• Automatic Memory Partitioning and Scheduling for Throughput and Power Optimization
• 564 IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS, VOL. 18, NO. 4, APRIL 2010 LOPASS: A Low-Power Architectural Synthesis
• Modeling and Layout Optimization of VLSI Devices and Interconnects In Deep Submicron Design
• Low-Power FPGA Using Pre-defined Dual-Vdd/Dual-Vt Fabrics
• 406 IEEE TRANSACTIONS ON COMPUTER-AIDED DESIGN OF INTEGRATED CIRCUITS AND SYSTEMS, VOL. 18, NO. 4, APRIL 1999 Theory and Algorithm of Local-Refinement-
• Fast Floorplanning by Look-Ahead Enabled Recursive Bipartitioning Jason Cong, Michail Romesis, and Joseph R. Shinnerl
• IEEE TRANSACTIONS ON COMPUTER-AIDED DESIGN OF INTEGRATED CIRCUITS AND SYSTEMS, VOL. 22, NO. 4, APRIL 2003 395 Multilevel Global Placement With
• Thermal-Driven Multilevel Routing for 3-D ICs Jason Cong and Yan Zhang
• Multi-level Placement for Large-Scale Mixed-Size IC Designs Chin-Chih Chang
• AN EFFICIENT TECHNIQUE FOR DEVICE AND INTERCONNECT OPTIMIZATION IN DEEP SUBMICRON DESIGNS
• Scheduling with Integer Time Budgeting for Low-Power Optimization Wei Jiang, Zhiru Zhang, Miodrag Potkonjak and Jason Cong
• 738 IEEE TRANSACTIONS ON COMPUTER-AIDED DESIGN OF INTEGRATED CIRCUITS AND SYSTEMS, VOL. 17, NO. 9, SEPTEMBER 1998 An Efficient Algorithm for Performance-Optimal
• Simultaneous Logic Decomposition with Technology Mapping in FPGA Designs
• 1268 IEEE TRANSACTIONS ON COMPUTER-AIDED DESIGN OF INTEGRATED CIRCUITS AND SYSTEMS, VOL. 19, NO. 11, NOVEMBER 2000 Performance-Driven Technology Mapping for
• Buffer Block Planning for Interconnect-Driven Floorplanning Jason Cong, Tianming Kong and David Zhigang Pan
• An Interconnect-Centric Design Flow for Nanometer Technologies
• Multiscale Optimization in VLSI Physical Design Automation
• IEEE TRANSACTIONS ON COMPUTER-AIDED DESIGN OF INTEGRATED CIRCUITS AND SYSTEMS, VOL. 23, NO. 4, APRIL 2004 537 Optimality and Scalability Study of Existing
• Synthesis of Reconfigurable High-Performance Multicore Jason Cong Karthik Gururaj Guoling Han
• Structural Gate Decomposition for Depth-Optimal Technology Mapping in LUT-based FPGA Design
• 1164 IEEE TRANSACTIONS ON COMPUTER-AIDED DESIGN OF INTEGRATED CIRCUITS AND SYSTEMS, VOL. 20, NO. 9, SEPTEMBER 2001 [18] B. Rohfleisch, B. Wurth, and K. Antreich, "Logic clause analysis for
• Simultaneous FU and Register Binding Based on Network Flow Method
• An Optimal Technology Mapping Algorithm for Delay Optimization in Lookup-Table Based FPGA Designs
• A Thermal-Driven Floorplanning Algorithm Jason Cong, Jie Wei, and Yan Zhang
• Highly Efficient Gradient Computation for Density-Constrained Analytical Placement Methods
• Pattern-Based Behavior Synthesis for FPGA Resource Reduction
• Customizable DomainSpecific Computing Jason Cong*
• Mapping for Better Than Worst-Case Delays In LUT-Based FPGA Designs
• A Reuse-Aware Prefetching Scheme for Scratchpad Jason Cong, Hui Huang, Chunyue Liu and Yi Zou
• mrFPGA: A Novel FPGA Architecture with Memristor-Based Reconfiguration
• Accelerating Fluid Registration Algorithm on Multi-FPGA Platforms Jason Cong, Muhuan Huang and Yi Zou
• EM+TV for Reconstruction of Cone-beam CT with Curved Detectors using GPU
• 3D Recursive Gaussian IIR on GPUs and FPGAs A Case Study for Accelerating Bandwidth-Bounded Applications
• Thermal-Aware Cell and Through-Silicon-Via Co-Placement for 3D ICs
• Accelerating Vision and Navigation Applications on a Customizable Platform
• Domain-Specific Processor with 3D Integration for Medical Image Processing
• Appears in ISVC 2011, Part I, LNCS 6938, pp. 1-10, 2011 EM+TV Based Reconstruction for Cone-Beam
• Utilizing RF-I and Intelligent Scheduling for Better Throughput/Watt in a Mobile GPU Memory System
• HC-Sim: A Fast and Exact L1 Cache Simulator with Scratchpad Memory Co-simulation Support
• Combined Loop Transformation and Hierarchy Allocation for Data Reuse Optimization
• Assuring Application-level Correctness Against Soft Errors Jason Cong and Karthik Gururaj
• An Energy-Efficient Adaptive Hybrid Cache Jason Cong, Karthik Gururaj, Hui Huang, Chunyue Liu, Glenn Reinman, Yi Zou
• DIMM0 DIMM1 DIMM2 DIMM3 DIMM0 DIMM1 DIMM2 DIMM3
• ATree-Based Topology Synthesis for On-Chip Network
• :2011-01-15;:2011-05-16 :""(No.2009ZX01036-001-003,No.2009ZX01029-001-002)
• Compilation and Architecture Support for Customized Vector Instruction Jason Cong, Mohammad Ali Ghodrat, Michael Gill, Hui Huang, Bin Liu, Raghu Prabhakar,
• An Integrated and Automated Memory Optimization Flow for FPGA Behavioral Synthesis
• 50 2012 IEEE International Solid-State Circuits Conference ISSCC 2012 / SESSION 2 / HIGH BANDWIDTH DRAM & PRAM / 2.7
• Platform Characterization for Domain-Specific Computing Kwang-Ting (Tim) Cheng,2
• 1490 IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS, VOL. 19, NO. 8, AUGUST 2011 An 8M Polygons/s 3-D Graphics SoC With Full Hardware
• FPGA-Accelerated 3D Reconstruction Using Compressive Sensing