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Nowatzyk, Andreas G. - Department of Electrical and Computer Engineering, Carnegie Mellon University
To Appear in the Sixth International Symposium on High-Performance Computer Architecture (HPCA), January 2000. Impact of Chip-Level Integration on
ited OWDM systems to small numbers of channels and to very high channel switching times [14,15].
ory. In this case, the entire system of TMC and TIC is con sidered. However, the TMC capacity limits the realizable
Verifying Distributed Directorybased Cache Coherence Protocols: S3.mp, a Case Study
8 Conclusion The trend towards larger DRAM devices exacerbates the
have very high latencies (>10 sec) and relatively low throughput (155 or 622 Mbits/sec). In addition, ATM sys
A Communication Architecture for Multiprocessor Networks
