
- Implementing Branch-Predictor Decay Using Quasi-Static Memory Cells
- A Supervised Learning Approach for Routing Optimizations in Wireless Sensor Networks
- Hardware Design Experiences in ZebraNet Pei Zhang, Christopher M. Sadler, Stephen A. Lyon, and Margaret Martonosi
- EnergyEfficient Computing for Wildlife Tracking: Design Tradeoffs and Early Experiences with ZebraNet
- Informing Memory Operations: Providing Memory Performance Feedback in Modern Processors
- Techniques for Multicore Thermal Management: Classification and New Exploration
- 02721732/05/$20.00 # 2005 IEEE Published by the IEEE computer Society Repetitive and recognizable phases
- The C-LINK System for Collaborative Web Usage: A Real-World Deployment in Rural Nicaragua
- Techniques for Multicore Thermal Management: Classification and New Exploration
- Exploring the Potential of CMP Core Count Management on Data Center Energy Savings
- Using Delayed Addition Techniques to Accelerate Integer and Floating Point Calculations in Configurable Hardware
- ISSCC 2003 / SESSION 9 / TD: DIGITAL ARCHITECTURE AND SYSTEMS / PAPER 9.5 9.5 Timekeeping Techniques for Predicting and
- Situation-Aware Caching Strategies in Highly Varying Mobile Networks Yong Wang, Margaret Martonosi, and Li-Shiuan Peh
- Adaptive Timekeeping Replacement: Fine-Grained Capacity Management for Shared CMP Caches
- Wattch: A Framework for Architectural-Level Power Analysis and Optimizations David Brooks Vivek Tiwari Margaret Martonosi
- HardwareModulated Parallelism in Chip Multiprocessors Julia Chen, Philo Juang, Kevin Ko,
- Recently, microprocessors have increasingly faced vexing power and thermal
- Implementing Application-Specific Cache-Coherence Protocols in Configurable Hardware
- CM226A-02 ACM-TRANSACTION August 11, 2004 19:6 Intraprogram Dynamic Voltage Scaling
- An Edge-Endpoint-Based Configurable Hardware Architecture for VLSI CAD Layout Design Rule Checking
- ISSCC 2003 / SESSION 9 / TD: DIGITAL ARCHITECTURE AND SYSTEMS / PAPER 9.5 9.5 Timekeeping Techniques for Predicting and
- Performance Monitoring in a Myrinet-Connected Shrimp Cluster Cheng Liao Margaret Martonosi Douglas W. Clark
- Using Reconfigurable Hardware to Customize Memory Hierarchies Peixin Zhong and Margaret Martonosi
- Accelerating Pipelined Integer and Floating-Point Accumulations in Configurable
- Applying Decay Strategies to Branch Predictors for Leakage Energy Savings Zhigang Hu
- Precise Miss Analysis for Program Transformations with Caches of Arbitrary Associativity
- DSPw orld, many mediaw orkloads have to perform a
- Monitoring Shared Virtual Memory Performance on a Myrinet-based PC Cluster Cheng Liao, Dongming Jiang, Liviu Iftode
- Managing the Cost, Energy Consumption, and Carbon Footprint of Internet Services
- Compile-Time Dynamic Voltage Scaling Settings: Opportunities and Limits
- Memory Referencing Behavior in CompilerParallelized Applications
- Adaptive Thermal Management for High-Performance Microprocessors David Brooks and Margaret Martonosi
- Limits and Graph Structure of Available InstructionLevel Parallelism
- Implementing Decay Techniques using 4T QuasiStatic Memory Cells
- Impala: A Middleware System for Managing Autonomic, Parallel Sensor Systems
- RegReS: Adaptively Maintaining a Target Density of Regional Services in Opportunistic Vehicular Networks.
- Draft submitted for publication. Please do not distribute Abstract--The speed of arithmetic calculations in
- Runtime Power Monitoring in High-End Processors: Methodology and Empirical Data
- Detecting Recurrent Phase Behavior under Real-System Variability Canturk Isci and Margaret Martonosi
- Informing Memory Operations: Providing Memory Performance Feedback in Modern Processors
- Solving Boolean Satisfiability with Dynamic Hardware Configurations
- Using Configurable Computing to Accelerate Boolean Satisfiability
- 02721732/06/$20.00 # 2006 IEEE Published by the IEEE computer Society Energy and power have become pri
- Power Prediction for Intel XScale r # Processors Using
- TCP: Tag Correlating Prefetchers T.J. Watson Research Center
- Middleware for Long-term Deployment of Delay-tolerant Sensor Networks
- TACO0801-05 ACM-TRANSACTION April 11, 2011 15:4 Parallelization Libraries: Characterizing and Reducing Overheads
- Improving Prediction for Procedure Returns with ReturnAddressStack Repair Mechanisms
- Effectiveness of Trace Sampling for Performance Debugging Tools Margaret Martonosi and Anoop Gupta
- Cache Miss Equations: A Compiler Framework for Analyzing and Tuning Memory Behavior
- Informing Memory Operations: Memory Performance Feedback Mechanisms and
- On Availability of Bitnarrow Operations in Generalpurpose Applications
- Supervised Learning in Sensor Networks: New Approaches with Routing, Reliability Optimizations
- Managing Leakage for Transient Data: Decay and QuasiStatic 4T Memory Cells
- Impala: A Middleware System for Managing Autonomic, Parallel Sensor Systems
- Coordinated, Distributed, Formal Energy Management of Chip Multiprocessors
- An Analysis of Efficient Multi-Core Global Power Management Policies: Maximizing Performance for a Given Power Budget
- Shared Last-Level TLBs for Chip Multiprocessors Abhishek Bhattacharjee
- A Comparison of Capacity Management Schemes for Shared CMP Caches Carole-Jean Wu and Margaret Martonosi
- Cache Miss Equations: A Compiler Framework for Analyzing and Tuning Memory Behavior
- Characterizing and Improving the Performance of Intel Threading Building Blocks
- Phase Characterization for Power: Evaluating Control-Flow-Based and Event-Counter-Based Techniques
- A Tale of Two Cities Sibren Isaacman
- Formal Online Methods for Voltage/Frequency Control in Multiple Clock Domain Microprocessors
- Accelerating Boolean Satisfiability with Configurable Hardware Peixin Zhong, Margaret Martonosi, Pranav Ashar \Lambda and Sharad Malik
- Pocket Cloudlets Emmanouil Koukoumidis
- Implementing Decay Techniques using Quasi-Static Memory Cells
- Transport Layer Approaches for Improving Idle Energy in Challenged Sensor Networks
- Characterizing the TLB Behavior of Emerging Parallel Workloads on Chip Multiprocessors
- THE TIMEKEEPING METHODOLOGY: EXPLOITING GENERATIONAL LIFETIME
- Tradeoffs in Message Passing and Shared Memory Implementations of a Standard Cell Router Margaret Martonosi and Anoop Gupta
- Evaluating the Impact of Advanced Memory Systems on CompilerParallelized Codes
- Reducing Register File Power Consumption by Exploiting Value Lifetime Characteristics
- An EdgeEndpointBased Configurable Hardware Architecture for VLSI CAD Layout Design Rule Checking
- Using Reconfigurable Computing Techniques to Accelerate Problems in the CAD Domain: A Case Study with Boolean Satisfiability
- Effectiveness of Trace Sampling for Performance Debugging Tools Margaret Martonosi and Anoop Gupta
- Tailoring Quantum Architectures to Implementation Style: A Quantum Computer for Mobile and Persistent Qubits
- Thread Criticality Predictors for Dynamic Performance, Power, and Resource Management in Chip Multiprocessors
- Tradeoffs in Message Passing and Shared Memory Implementations of a Standard Cell Router Margaret Martonosi and Anoop Gupta
- MARio: Mobility-Adaptive Routing Using Route Lifetime Abstractions in Mobile Ad Hoc Networks
- CM226A02 ACMTRANSACTION August 11, 2004 19:6 Intraprogram Dynamic Voltage Scaling
- Potential for Collaborative Caching and Prefetching in Largely-Disconnected Villages
- Dynamically Exploiting Narrow Width Operands to Improve Processor Power and Performance
- Phase Characterization for Power: Evaluating ControlFlowBased and EventCounterBased Techniques
- Voltage and Frequency Control With Adaptive Reaction Time in MultipleClockDomain Processors
- Coordinated, Distributed, Formal Energy Management of Chip Multiprocessors
- Cache Miss Equations: An Analytical Representation of Cache Misses
- Limits and Graph Structure of Available Instruction-Level Parallelism
- 0018-9162/97/$10.00 1997 IEEE44 Computer Shared Memory
- SRC Student Symposium 2006 Technical Paper Form Presentation Title: Phase Detection and Prediction on Real Systems for Workload-Adaptive Power
- Capping the Brown Energy Consumption of Internet Services at Low Cost
- Power dissipation limits have emerged as a major constraint in the design
- A Mathematical Cache Miss Analysis for Pointer Data Structures Hongli Zhang and Margaret Martonosi
- Energy Adaptation Techniques to Optimize Data Delivery in Store-and-Forward Sensor Networks
- Identifying Important Places in People's Lives from Cellular Network Data
- Characterization and Dynamic Mitigation of Intra-Application Cache Interference
- Low-Infrastructure Methods to Improve Internet Access for Mobile Users in Emerging Regions
- Full-System Chip Multiprocessor Power Evaluations Using FPGA-Based Emulation
- LOCALE: Collaborative Localization Estimation for Sparse Mobile Sensor Networks
- Location-based Trust for Mobile User-generated Content: Applications, Challenges and Implementations
- A Combinatorial Noise Model for Quantum Computer Simulation Eric Chi, Stephen A. Lyon, Margaret Martonosi
- The XTREM Power and Performance Simulator for the Intel XScaleR
- Live, Runtime Phase Monitoring and Prediction on Real Systems with Application to Dynamic Power Management
- Data Compression Algorithms for Energy-Constrained Devices in Delay Tolerant Networks
- Techniques for Real-System Characterization of Java Virtual Machine Energy and Power Behavior
- Power Efficiency for Variation-Tolerant Multicore Processors
- This article has been accepted for inclusion in a future issue of this journal. Content is final as presented, with the exception of pagination. An Efficient, Practical Parallelization Methodology
- 1190272-1732/06/$20.00 2006 IEEE Published by the IEEE computer Society Energy and power have become pri-
- Hardware-Modulated Parallelism in Chip Multiprocessors Julia Chen, Philo Juang, Kevin Ko,
- Power Prediction for Intel XScaler Processors Using Performance Monitoring Unit Events
- Bounds on Power Savings Using Runtime Dynamic Voltage Scaling: An Exact Algorithm and a Linear-time
- Erasure-Coding Based Routing for Opportunistic Networks Yong Wang, Sushant Jain
- Leveraging Simultaneous Multithreading for Adaptive Thermal Control
- Voltage and Frequency Control With Adaptive Reaction Time in Multiple-Clock-Domain Processors
- Formal Online Methods for Voltage/Frequency Control in Multiple Clock Domain Microprocessors
- XTREM: A Power Simulator for the Intel XScaler Core Gilberto Contreras, Margaret Martonosi
- THE TIMEKEEPING METHODOLOGY: EXPLOITING GENERATIONAL LIFETIME
- Managing Leakage for Transient Data: Decay and Quasi-Static 4T Memory Cells
- In the DSP world, many media workloads have to perform a specific amount of work in a specific period of time. This
- An Adaptive Issue Queue for Reduced Power at High Performance Alper Buyuktosunoglu*, 2
- On Availability of Bit-narrow Operations in General-purpose Applications
- Augmenting Modern Superscalar Architectures with Configurable Extended Instructions
- MemSpy: Analyzing Memory System Bottlenecks in Programs Margaret Martonosi and Anoop Gupta
- Static Timing Analysis of Embedded Software Sharad Malik Margaret Martonosi
- Informing Memory Operations: Memory Performance Feedback Mechanisms and
- doi: 10.1098/rsta.2008.0127 , 3699-37083662008Phil. Trans. R. Soc. A
- Accelerating Pipelined Integer and Floating-Point Accumulations in Configurable
- Implementing ApplicationSpecific CacheCoherence Protocols in Configurable Hardware
- TemperatureAware Design Issues for SMT and CMP Architectures James Donald and Margaret Martonosi
- PowerPerformance Modeling and Tradeoff Analysis for a High End Microprocessor
- Integrating Performance Monitoring and Communication in Parallel Computers
- Inter-Core Cooperative TLB Prefetchers for Chip Multiprocessors
- Leveraging Simultaneous Multithreading for Adaptive Thermal Control
- Characterizing the Memory Behavior of CompilerParallelized Applications
- Bounds on Power Savings Using Runtime Dynamic Voltage Scaling: An Exact Algorithm and a Lineartime
- Improving Prediction for Procedure Returns with Return-Address-Stack Repair Mechanisms
- Recently, microprocessors have increasingly faced vexing power and thermal
- Multipath Execution: Opportunities and Limits Pritpal S. Ahuja, Kevin Skadron, Margaret Martonosi
- Static Timing Analysis of Embedded Software Sharad Malik Margaret Martonosi
- Timekeeping in the Memory System: Predicting and Optimizing Memory Behavior
- Applying Decay Strategies to Branch Predictors for Leakage Energy Savings Zhigang Hu y Philo Juang y Kevin Skadron z Doug Clark Margaret Martonosi y
- Dynamic Thermal Management for HighPerformance Microprocessors David Brooks
- CompileTime Dynamic Voltage Scaling Settings: Opportunities and Limits
- A Dynamic Compilation Framework for Controlling Microprocessor Energy and Performance
- Implementing Software on Resource-Constrained Mobile Sensors: Experiences with Impala and ZebraNet
- 00189162/97/$10.00 1997 IEEE 44 Computer
- A Dynamic Compilation Framework for Controlling Microprocessor Energy and Performance
- Wavelet Analysis for Microprocessor Design: Experiences with WaveletBased dI/dt Characterization
- Adaptive Parallelism in CompilerParallelized Code Mary W. Hall \Lambda
- 390272-1732/05/$20.00 2005 IEEE Published by the IEEE computer Society Repetitive and recognizable phases
- Temperature-Aware Design Issues for SMT and CMP Architectures James Donald and Margaret Martonosi
- Identifying Program Power Phase Behavior Using Power Vectors Canturk Isci and Margaret Martonosi
- Augmenting Modern Superscalar Architectures with Configurable Extended Instructions
- XTREM: A Power Simulator for the Intel XScale r Gilberto Contreras, Margaret Martonosi
- Let Caches Decay: Reducing Leakage Energy via Exploitation of Cache Generational Behavior
- Precise Miss Analysis for Program Transformations with Caches of Arbitrary Associativity
- IEEE TRANSACTIONS ON MOBILE COMPUTING 1 Leveraging Smartphone Cameras for