Chu, Chris C.-N. - Department of Electrical and Computer Engineering, Iowa State University

• An Efficient Analytical Placement Algorithm for Mixed-Mode Designs in the presence of Placement Blockages
• IEEE TRANSACTIONS ON COMPUTER-AIDED DESIGN OF INTEGRATED CIRCUITS AND SYSTEMS, VOL. 18, NO. 9, SEPTEMBER 1999 1297 An Efficient and Optimal Algorithm for
• Optimal Gate Sizing for Coupling-Noise Reduction Debjit Sinha, Hai Zhou
• Fast and Exact Simultaneous Gate and Wire Sizing by Lagrangian Relaxation Chung-Ping Chen y
• Simultaneous Driver Sizing and Buffer Insertion Using a Delay Penalty Estimation Technique
• IEEE TRANSACTIONS ON COMPUTER-AIDED DESIGN OF INTEGRATED CIRCUITS AND SYSTEMS, VOL. 20, NO. 5, MAY 2001 687 Handling Soft Modules in General Nonslicing Floorplan
• IEEE TRANSACTIONS ON COMPUTER-AIDED DESIGN OF INTEGRATED CIRCUITS AND SYSTEMS, VOL. 29, NO. 3, MARCH 2010 367 DeFer: Deferred Decision Making Enabled
• Fitted Elmore Delay: A Simple and Accurate Interconnect Delay Model Arif Ishaq Abou-Seido
• Post-Placement Voltage Island Generation Royce L.S. Ching, Evangeline F.Y. Young,
• JOURNAL OF LATEX CLASS FILES, VOL. 6, NO. 1, JANUARY 2007 1 Wire Retiming Problem with Net Topology
• A Unified Method to Handle Different Kinds of Placement Constraints in Floorplan Design
• Twin Binary Sequences: A Non-redundant Representation for General Non-slicing Floorplan
• 1014 IEEE TRANSACTIONS ON COMPUTER-AIDED DESIGN OF INTEGRATED CIRCUITS AND SYSTEMS, VOL. 18, NO. 7, JULY 1999 Fast and Exact Simultaneous Gate and Wire Sizing
• Retiming with Interconnect and Gate Delay Chris Chu, Evangeline F. Y. Young, Dennis K. Y. Tong, and Sampath Dechu
• Physical Synthesis Comes of Age Charles J. Alpert
• FastPlace 2.0: An Efficient Analytical Placer for Mixed-Mode Designs Natarajan Viswanathan, Min Pan and Chris Chu
• FastRoute 4.0: Global Router with Efficient Via Minimization Yue Xu, Yanheng Zhang and Chris Chu
• A Revisit to Floorplan Optimization by Lagrangian Magma Design Automation
• Floorplan Area Minimization using Lagrangian Relaxation F.Y. Young1
• Timing Yield Estimation Using Statistical Static Timing Analysis , Chris Chong-Nuen Chu1
• FastPlace: Efficient Analytical Placement using Cell Shifting, Iterative Local Refinement and a Hybrid Net Model
• GREMA: Graph Reduction Based Efficient Mask Assignment for Double Patterning Technology
• Generation of Universal Series-Parallel Boolean F. Y. YOUNG, CHRIS C. N. CHU, AND D. F. WONG
• An Efficient Routing Tree Construction Algorithm with Buffer Insertion, Wire Sizing and
• FastRoute3.0: A Fast and High Quality Global Router Based on Virtual Capacity
• 680 IEEE TRANSACTIONS ON COMPUTER-AIDED DESIGN OF INTEGRATED CIRCUITS AND SYSTEMS, VOL. 20, NO. 5, MAY 2001 Hybrid Dynamic/Quadratic Programming Algorithm for
• IEEE TRANSACTIONS ON VLSI SYSTEMS, 2004 1 Fitted Elmore Delay: A Simple and Accurate
• A New Approach to Simultaneous Bu er Insertion and Wire Sizing Chris C. N. Chu and D. F. Wong
• CLOSED FORM SOLUTION TO SIMULTANEOUS BUFFER INSERTION/SIZING AND WIRE SIZING
• Annals of Operations Research 105, 3760, 2001 2002 Kluwer Academic Publishers. Manufactured in The Netherlands.
• Author's personal copy Handling routability in floorplan design with twin binary trees$
• Accurate and Efficient Flow based Congestion Estimation in Floorplanning
• A MATRIX SYNTHESIS APPROACH TO THERMAL PLACEMENT Chris C. N. Chu and D. F. Wong
• A Matching Based Decomposer for Double Patterning Lithography
• ITOP: Integrating Timing Optimization within Placement Natarajan Viswanathan
• 1166 IEEE TRANSACTIONS ON COMPUTER-AIDED DESIGN OF INTEGRATED CIRCUITS AND SYSTEMS, VOL. 17, NO. 11, NOVEMBER 1998 A Matrix Synthesis Approach to Thermal Placement
• 398 IEEE TRANSACTIONS ON COMPUTER-AIDED DESIGN OF INTEGRATED CIRCUITS AND SYSTEMS, VOL. 18, NO. 4, APRIL 1999 Greedy Wire-Sizing Is Linear Time
• IEEE TRANSACTIONS ON COMPUTER-AIDED DESIGN OF INTEGRATED CIRCUITS AND SYSTEMS, VOL. 18, NO. 6, JUNE 1999 787 A Quadratic Programming Approach to Simultaneous
• Closed Form Solution to Simultaneous Buffer Insertion/Sizing and Wire Sizing
• 1354 IEEE TRANSACTIONS ON COMPUTER-AIDED DESIGN OF INTEGRATED CIRCUITS AND SYSTEMS, VOL. 22, NO. 10, OCTOBER 2003 Bounds on the Number of Slicing, Mosaic, and
• Non-Rectangular Shaping and Sizing of Soft Modules for Floorplan Design Improvement
• Simultaneous Driver Sizing and Buffer Insertion Using a Delay Penalty Estimation Technique
• IEEE TRANSACTIONS ON COMPUTER-AIDED DESIGN OF INTEGRATED CIRCUITS AND SYSTEMS, VOL. XX, NO. Y, MONTH 2005 1 FastPlace: Efficient Analytical Placement using Cell Shifting,
• OPTIMIZING SOC TEST RESOURCES USING DUAL SEQUENCES
• IEEE TRANSACTIONS ON COMPUTER-AIDED DESIGN, 2007 1 FLUTE: Fast Lookup Table Based Rectilinear
• IEEE TRANSACTIONS ON COMPUTER-AIDED DESIGN, 2011 1 SafeChoice: A Novel Approach to Hypergraph
• Dilation-5 Embedding of 3-Dimensional Grids into Hypercubes M.Y. Chan, F. Chin, C.N. Chu and W.K. Mak
• A Polynomial Time Optimal Algorithm for Simultaneous Bu er and Wire Sizing
• GREEDY WIRE-SIZING IS LINEAR TIME Chris C. N. Chu and D. F. Wong
• A Hybrid Dynamic/Quadratic Programming Algorithm for Interconnect Tree Optimization
• Non-Rectangular Shaping and Sizing of Soft Modules for Floorplan Design Improvement
• A New and Efficient Congestion Evaluation Model in Floorplanning: Wire Density Control with Twin Binary Trees
• Optimizing SOC Test Resources using Dual Sequences In this paper, we propose a new data structure called
• An Efficient Routing Tree Construction Algorithm with Buffer Insertion, Wire Sizing and Obstacle Considerations
• Transition Time Bounded Low-power Clock Tree Construction Min Pan, Chris Chong-Nuen Chu and J. Morris Chang
• Fast and Accurate Rectilinear Steiner Minimal Tree Algorithm for VLSI Design
• Efficient Rectilinear Steiner Tree Construction with Rectilinear Blockages
• An Efficient and Effective Detailed Placement Min Pan, Natarajan Viswanathan and Chris Chu
• FastRoute: A Step to Integrate Global Routing into Placement Min Pan and Chris Chu
• Analog Placement with Symmetry and Other Placement Constraints
• A Novel Performance-Driven Topology Design Algorithm Min Pan, Chris Chu Priyadarshan Patra
• FastRoute 2.0: A High-quality and Efficient Global Router Min Pan, and Chris Chu
• FastPlace 3.0: A Fast Multilevel Quadratic Placement Algorithm with Placement Congestion Control
• A Scalable and Accurate Rectilinear Steiner Minimal Tree Algorithm Yiu-Chung Wong
• DeFer: Deferred Decision Making Enabled Fixed-Outline Floorplanner Jackey Z. Yan Chris Chu
• Pad Assignment for Die-Stacking System-in-Package Design
• FOARS: FLUTE Based Obstacle-Avoiding Rectilinear Steiner Tree Construction
• SafeChoice: A Novel Clustering Algorithm for Wirelength-Driven Placement Jackey Z. Yan
• An Auction Based Pre-Processing Technique to Determine Detour in Global Routing
• RegularRoute: An Efficient Detailed Router with Regular Routing Patterns Yanheng Zhang and Chris Chu
• Twin Binary Sequences: A Non-Redundant Representation
• RQL: Global Placement via Relaxed Quadratic Spreading and Linearization
• FLUTE: Fast Lookup Table Based Wirelength Estimation Technique Electrical and Computer Engineering
• IPR: An Integrated Placement and Routing Algorithm Min Pan Chris Chu
• IEEE TRANSACTIONS ON VLSI SYSTEMS, 2004 1 Placement Constraints in Floorplan Design
• ISPD: FOARS: FLUTE Based Obstacle-Avoiding Rectilinear Steiner Tree Construction
• Handling Uncertainty article, 7/23/2003 1 Reliable Computing 9, pp. 1-12, 2003.
• Handling Complexities in Modern Large-Scale Mixed-Size Placement Jackey Z. Yan Natarajan Viswanathan Chris Chu
• A Simple Fast Exact Density Calculation Algorithm Hua Xiang Chris Chu Ruchir Puri
• CROP: Fast and Effective Congestion Refinement of Placement Yanheng Zhang and Chris Chu
• MGR: Multi-Level Global Router Yue Xu and Chris Chu