- Reducing DRAM Latencies with an Integrated Memory Hierarchy Design This work is supported in part by the National Science Foundation under
- Efficient Synchronization: Let Them Eat QOLB1 Alain Kgi, Doug Burger, and James R. Goodman
- Memory Systems Doug Burger
- An Adaptive Cache Structure for Future High-Performance Systems Changkyu Kim Doug Burger Stephen W. Keckler
- Designing a Modern Memory Hierarchy with Hardware Prefetching
- The Declining Effectiveness of Dynamic Caching for General-Purpose Microprocessors
- HARDWARE TECHNIQUES TO IMPROVE THE PERFORMANCE OF THE PROCESSOR/MEMORY INTERFACE
- Memory Bandwidth Limitations of Future Microprocessors Doug Burger, James R. Goodman, and Alain Kgi
- The SimpleScalar Tool Set, Version 2.0 *Contact: dburger@cs.wisc.edu
- 0018-9162/97/$10.00 1997 IEEE December 1997 51 Changing Interaction
- Appears in the Proceedings of the 10 International Conference on Architectural Support for Programming Languages and Operating Systems (ASPLOS)
- Measuring Experimental Error in Microprocessor Simulation Rajagopalan Desikan*
- Bottlenecks in Multimedia Processing with SIMD style Extensions and Architectural Enhancements
- 0272-1732/97/$10.00 1997 IEEE November/December 1997 55 The phenomenal improvements in
- Memory Systems Doug Burger
- Appears in the Proceedings of the 34 Annual Workshop on Workload Characterization
- Appears in the 5th Annual Workshop on Interaction between Compilers and Computer Architectures (INTERACT-5) A Technology-Scalable Architecture for Fast Clocks and High ILP
- Static Energy Reduction Techniques in Microprocessor Caches Heather Hanson, Stephen W. Keckler, Doug Burger
- ISSCC 2003 / SESSION 9 / TD: DIGITAL ARCHITECTURE AND SYSTEMS / PAPER 9.6 9.6 A Wire-Delay Scalable Microprocessor
- Appears in the International Conference on Computer Design
- 0018-9162/97/$10.00 1997 IEEE46 Computer Billion-Transistor
- Doug Burger Computer Sciences Department
- Modeling the Impact of Device and Pipeline Scaling on the Soft Error Rate of Processor Elements
- Appears in the 13th International Conference on Parallel Architecture and Compilation Techniques (PACT 2004) Static Placement, Dynamic Issue (SPDI) Scheduling for EDGE Architectures
- Guided Region Prefetching: A Cooperative Hardware/Software Approach
- Appears in the Annual International Symposium on Microarchitecture
- Appears in the International Conference on Computer Design
- Appears in the Annual International Symposium on Microarchitecture
- Appears in the Annual International Symposium on Computer Architecture
- IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION, VOL. XX, NO. Y, MONTH, YEAR 1 Static Energy Reduction Techniques for
- DataScalar Architectures Doug Burger, Stefanos Kaxiras, and James R. Goodman
- Exploiting Optical Interconnects to Eliminate Serial Bottlenecks Doug Burger and James R. Goodman
- Appears in the Proceedings of the 34 Annual International Symposium on Microarchitecture
- Accuracy vs. Performance in Parallel Simulation of Interconnection Networks Douglas C. Burger and David A. Wood
- Appears in the 11th International Conference on Architectural Support for Programming Languages and Operating Systems Scalable Selective Re-Execution for EDGE Architectures
- System-Level Implications of Processor-Memory Integration Doug Burger
- Simulation of the SCI Transport Layer on the Wisconsin Wind Tunnel Douglas C. Burger and James R. Goodman
- Appears in the Proceedings of the 2001 International Conference on Computer Design Static Energy Reduction Techniques for Microprocessor Caches
- Techniques for Reducing Overheads of Shared-Memory Multiprocessing
- A previous evaluation of scheduled region prefetching showed that this technique eliminates the bulk of main-
