
- Abstract -In this paper, new formulations for the energy dissipation of lossy transmission lines driven by CMOS inverters are provided, and a new
- A Novel High Frequency, High-Efficiency, Differential Class-E Power Amplifier in 0.18m CMOS
- Abstract -This paper investigates important problems involved in the design of a CML buffer as well as a chain of
- Abstract -This work presents accurate closed-form expressions for the interconnect energy dissipation in high-speed ULSI circuits.
- Abstract -This paper presents a spectrally-weighted balanced truncation technique for RLC interconnects, a technique needed when the intercon-
- Abstract-CMOS Phase-locked loops (PLL) are ubiquitous in RF and mixed-signal integrated circuits. PLLs are very sensitive
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- 618 IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS, VOL. 13, NO. 5, MAY 2005 Design and Analysis of an Ultrawide-Band
- Abstract -A comprehensive study of ultra high-speed current-mode logic (CML) buffers and regenerative CML latches will
- Abstract-This paper presents a detailed empirical study and analyti-cal derivation of voltage wave-form and energy dissipation of global
- 10 2005 IEEE International Solid-State Circuits Conference 0-000-000-0/00/$10.00 2005 IEEE ISSCC 2005 / SESSION 8 / CIRCUITS FOR HIGH-SPEED LINKS AND CLOCK-GENERATORS / 8.4
- Abstract -A new analytical model for high-frequency noise in RF active CMOS mixers such as single-balanced and dou-
- IEEE JOURNAL OF SOLID-STATE CIRCUITS, VOL. 42, NO. 9, SEPTEMBER 2007 1 Design and Analysis of a Performance-Optimized
- Design and Analysis of a Distributed Regenerative Frequency Divider Using a Distributed Mixer
- A Novel Ultra High-Speed Flip-Flop-Based Frequency Divider Ravindran Mohanavelu and Payam Heydari
- Abstract -A current-mode logic (CML) buffer is based on a simple differential circuit. This paper investigates important
- Abstract -Substrate noise is the major source of performance limitation in mixed-signal integrated circuits. This paper studies
- Abstract--Scaling the minimum feature size of VLSI circuits to sub-quar-ter micron and its clock frequency to 2GHz has caused crosstalk noise to
- Abstract--This paper is concerned with the analysis and optimization of the ground bounce in digital CMOS circuits. First, an analytical
- Abstract-Phase-locked loops (PLL) in RF and mixed signal VLSI circuits experience supply noise which translates to a timing jitter.
- Abstract-In this paper, we present a new analytical approach for computing the ramp response of an RLC interconnect line with a
- Abstract -In this paper, new formulations for the energy dissipation of lossy transmission lines driven by CMOS inverters are provided. These
- Abstract-This paper presents a numerically stable and efficient algorithm for model reduction of large RLC net-
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