Thornton, Mitchell - Computer Science and Engineering Department, Southern Methodist University

• Quaternary Addition Circuits Based on SUSLOC Voltage-Mode Cells and Modeling with SystemVerilog
• An FPGA Approach for SNR Estimation Using PhaseOnly A thesis submitted in partial fulfillment
• Performance Enhancement in Phased Logic Circuits Using Automatic Slack-matching Buffer Insertion
• A Signed Binary Addition Circuit Based on an Alternative Class of Addition Tables
• Low Power Optimization Technique for BDD Mapped Circuits Per Lindgren Mikael Kerttu Mitch Thornton
• Proceedings of the 2004 American Society for Engineering Education Midwest Section ASEE Midwest Section Meeting
• Page 1 of 12 A COMPLIANCE FRAMEWORK TO OPTIMIZE PRODUCT DEVELOPMENT IN A
• A Framework and Process for Curricular Integration and Innovation Using Project Based Interdisciplinary Teams
• Submitted to Electronics Letters A FAST TWO-PHASE MICROPIPELINE CONTROL
• Modified Haar Transform Calculation Using Digital Circuit Output Probabilities \Lambda
• MDDBased Synthesis of MultiValued Logic Networks Rolf Drechsler Mitch Thornton David Wessels
• [11] R. E. Bryant. GraphBased Algorithms for Boolean Function Manipulation. IEEE Transactions on Computers, vol. C35, no. 8:677--691, August 1986.
• IMPLEMENTATION OF COMPILER, VIEWER, AND PARALLELISM ANALYSIS SOFTWARE
• CROSSTALK DELAY ANALYSIS IN VERY DEEP SUB MICRON VLSI CIRCUITS
• A Technique for Multiprocessor Memory Resource Estimation ** J. D. Bullard M. A. Thornton D. L. Andrews
• Logic Circuit Equivalence Checking Using Haar Spectral Coecients and Partial BDDs
• Low Power Optimization Techniques for BDD Mapped Circuits Using
• Abstract--This work presents an improved design for a carry-free adder featuring on-line error detection. The salient
• 2001 ASEE Southeast Section Conference UNIX Scripting and High-level Language Education Using
• Computation of Spectral Information from Logic Netlists Rolf Drechsler Mitch Thornton
• UNIX and Highlevel Language Education Using Windows Operating Systems
• Resource Estimation for Parallel Architectures with Distributed Processor/Memory Nodes **
• PLFire: A Visualization Tool for Asynchronous Phased Logic Designs K. Fazel, M. A. Thornton R. B. Reese
• Efficient Calculation of Spectral Coefficients and Their Applications \Lambda
• ACKNOWLEDGEMENTS I would like to think my thesis advisor, Dr. Thornton, for the opportunity to work on this
• Parity Function Detection and Realization Using a Small Set of Spectral Coefficients \Lambda
• A BDD Variable Reordering Heuristic Based on Output Probability Periodicity
• Addition-based exponentiation modulo 2k A. Fit-Florea, D.W. Matula and M.A. Thornton
• Keyboard Dynamics Mitchell A. Thornton
• Early Evaluation for Performance Enhancement in Phased Logic Robert B. Reese, Mississippi State University (reese@ece.msstate.edu)
• A Digit Serial Algorithm for the Integer Power Operation Southern Methodist University
• COMPUTER-AIDED-DESIGN METHODS FOR EMERGING QUANTUM COMPUTING
• A SPLIT DATA CACHE ORGANIZATION BASED ON RUNTIME DATA LOCALITY ESTIMATION
• Fast ReedMuller Spectrum Computation Using Output Probabilities \Lambda
• Table 3: Results of the Probability Based Heuristic Method for DD Reordering
• A Method for Approximate Equivalence Checking Mitch Thornton Rolf Drechsler Wolfgang Gunther
• Abstract--Decision diagrams provide compact representations for discrete functions. There are some functions for which
• BDD-BASED CONJUNCTIVE DECOMPOSITION USING A GENETIC ALGORITHM AND DEPENDENT VARIABLE AFFINITY
• Evaluation of Toggle Coverage for MVL Circuits Specified in the SystemVerilog HDL
• A Numerical Method for ReedMuller Circuit Synthesis
• Boolean Function Spectrum Computation Using a Structural Representation
• Multiprocessor Resource Estimation Using a Stochastic Modeling Approach D. L. Andrews, M. A. Thornton, J. D. Bullard
• AxiomaticAnalysisandCyberThreatTreeModelsfortheDevelopmentofLargeScaleDisaster TolerantInformationSecuritySystems
• Combining Simulation and Formal Verification for Integrated Circuit Design Validation Lun Li, Stephen A. Szygenda, Mitchell A. Thornton
• Table 5: Processing Activity Under Transformed Thread Sequenced Prescheduling
• Applications and Efficient Computation of Spectral Coefficients for Digital Logic
• IEEE TRANSACTIONS ON COMPUTERS, VOL. 46, NO. 7, JULY 1997 1 J:\PRODUCTION\TC\2
• Variable Reordering for Shared Binary Decision Diagrams Using Output Probabilities* M. A. Thornton + , J. P. Williams R. Drechsler # , N. Drechsler #
• Disaster Tolerant Computer and Communication Systems Stephen A. SZYGENDA
• Submitted to Electronics Letters A TWO-PHASE MICROPIPELINE CONTROL WRAPPER FOR
• Application of a Hardware Synthesis Technique for Database Query Optimization*
• An Overview of Placement and Routing Algorithms for PCB, VLSI, and MCM Designs
• Performance Evaluation of a Novel Direct Table Lookup Method and Architecture With Application to 16-bit Integer Functions
• Abstract--Large, established systems are essentially impossible to replace and must be improved incrementally to incorporate
• Behavioral to Structural Translation in ESOP Form M. A. Thornton, V. S. S. Nair
• Boolean Function Representation and Spectral Characterization Using AND/OR Graphs \Lambda
• Binary Decision Diagram Visualization: A Research Experience for Undergraduates **
• Principle Investigator/Project Director: Mitchell A. Thornton Institution: Southern Methodist University
• no computational degradation. 0 1 2 3 4 5 6 7 8 9 10
• Extracting Spectral Information from AND/OR Representations M. A. Thornton R. Drechsler A.
• Toffoli Gate Cascade Generation Using ESOP Minimization and QMDD-based Dept. of Mathematics & Computer Science
• Quantum Logic Circuit Simulation Based on the QMDD Data Structure David Goodman, Mitchell A. Thornton, David Y. Feinstein D. Michael Miller
• Abstract--Redundant signed binary addition (RSBA) has been used to create high performance arithmetic circuits.
• A Coarse-Grain Phased Logic CPU Abstract: A five-stage pipelined CPU based on the MIPs ISA is mapped to a self-timed
• 9/3/09 8:07 AMIEEE-USA Today's Engineer Page 1 of 4http://www.todaysengineer.org/2009/Sep/Software-PE.asp
• Early Evaluation for Phased Logic Circuits Using BDDs and MVL* Kenneth Fazel, Mitchell A. Thornton Robert B. Reese
• Figure 6: Final Circuit using MultiLevel Design Process Combine F(x)
• Low-power optimization techniques for BDD mapped circuits using temporal correlation
• A Genetic Approach for Conjunction Scheduling in Symbolic Equivalence Checking
• Probabilistic Equivalence Checking Using Partial Haar Spectral Diagrams \Lambda
• Transformations Amongst the Walsh, Haar, Arithmetic and Reed-Muller Spectral Domains
• Spectral Decision Diagrams Using Graph Transformations Mitchell Thornton Rolf Drechsler
• "MVLSC" --"ismvl-7" --2009/1/27 --13:44 --page 1 --#1 J. of Mult.-Valued Logic & Soft Computing, Vol. 00, pp. 117 2009 Old City Publishing, Inc.
• A Redundant Signed Binary Addition Based Digital-to-Frequency Converter
• A Methodology for Disaster Tolerance Utilizing the Concepts of Axiomatic Design
• Components of Disaster Tolerant Computing: Analysis of Disaster Recovery, IT Application
• Spectral Analysis of Digital Logic Using Circuit Netlists Mitchell A. Thornton
• Quaternary Voltage-Mode Logic Cells and Fixed-Point Multiplication Circuits*
• A Low Power High Performance Radix-4 Approximate Squaring Circuit Satyendra R. Datla Mitchell A. Thornton David W. Matula
• On the Guidance of Reversible Logic Synthesis by Dynamic Variable Reordering David Y. Feinstein Mitchell A. Thornton
• Partially Redundant Logic Detection Using Symbolic Equivalence Checking in Reversible and Irreversible Logic Circuits
• ESOP-based Toffoli Gate Cascade Generation K. Fazel, M. A. Thornton
• Axiomatic Design Process for Disaster Tolerance Diana EASTON
• Variable Reordering and Sifting for QMDD D. Michael Miller David Y. Feinstein and Mitchell A. Thornton
• Techniques for Disaster Tolerant Information Technology Systems
• A Quantum CAD Accelerator Based on Grover's Algorithm for Finding the Minimum Fixed Polarity Reed-Muller Form
• IT Application Downtime, Executive Visibility and Disaster Tolerant Computing
• The Karhunen-Lo`eve Transform of Discrete MVL Functions Mitchell Aaron Thornton
• Hardware Implementation of an Additive Bit-Serial Algorithm for the Discrete Logarithm Modulo 2k
• From UML to HDL: a Model Driven Architectural Approach to Hardware-Software Co-Design
• TEST VECTOR GENERATION AND CLASSIFICATION USING FSM TRAVERSALS Ralph Marczynski, Mitchell A. Thornton, Stephen A. Szygenda
• A Fine-Grain Phased Logic CPU Robert B. Reese Mitchell A. Thornton Cherrice Traver
• Computing Walsh, Arithmetic, and Reed-Muller Spectral Decision Diagrams Using
• Multi-output Timed Shannon Circuits Mitchell A. Thornton Rolf Drechsler D. Michael Miller
• Generalized Early Evaluation in Self-timed Circuits M. A. Thornton, K. Fazel, R. B. Reese C. Traver
• Abstract--A self-timed programmable architecture used for the implementation of Phased Logic (PL) systems is described.
• A logic style known as Phased Logic(PL) is applied to arithmetic circuits. Phased logic is a dual-rail LEDR logic style that allows
• Abstract--The Walsh spectrum for a Boolean function has found many uses in VLSI CAD. A graph-based approach to
• Low Power Optimization Technique for BDD Mapped Circuits Per Lindgren Mikael Kerttu Mitch Thornton Rolf Drechsler
• SYSTEM-ON-CHIP POWER CONSUMPTION REFINEMENT AND David Y. Feinstein, Mitchell A. Thornton and Fatih Kocan
• ESOP Transformation to Majority Gates for Quantum-dot Cellular Automata Logic Synthesis
• Boolean Function Matching using Walsh Spectral Decision Diagrams Jason Moore, Kenneth Fazel, Mitchell A. Thornton D. Michael Miller
• Teaching a Laboratory Intensive Class in a Distance Education Mode
• Perl for Introductory Programming Courses Jason Moore, Mitchell A. Thornton Ronald W. Skeith
• Prefix Parallel Adder Virtual Implementation in Reversible Logic
• Multilevel Variable Length Shifter Design for an Iterated Shift-and-Add Product Operation
• "Proceedings of the 2006 Midwest Section Conference of the American Society for Engineering Encouraging Computer Engineering Students to Take the Fundamentals of
• 8/21/09 10:38 AMIEEE-USA Today's Engineer Page 1 of 5http://www.todaysengineer.org/2009/Jun/FE-Exam.asp
• ASEE Southeast Section Conference A Second Undergraduate Course in Digital Logic Design
• HARDWARE ACCELERATION OF SOFTWARE LIBRARY STRING FUNCTIONS
• INTEGRATED TECHNIQUES FOR THE FORMAL VERIFICATION AND VALIDATION
• PERFORMANCE ENHANCEMENT TECHNIQUES FOR PHASED LOGIC CIRCUITS
• ESOP CIRCUIT MINIMIZATION BASED ON THE FUNCTION ON-SET
• !!!!!!!! NEW COURSE ANNOUNCEMENT !!!!!!!! Distance and On-Campus Sections Available
• G e n e r a l I n f o r m a t I o n U n d e r G r a d U a t e C a t a l o G
• 2 Copublished by the IEEE CS and the AIP 1521-9615/10/$26.00 2010 IEEE Computing in SCienCe & engineering E d u C A t I o n
• A Discrete Logarithm Number System for Integer Arithmetic Modulo 2k
• QMDD Minimization using Sifting for Variable Reordering
• On the Skipped Variables of Quantum Multiple-valued Decision Diagrams David Y. Feinstein Mitchell A. Thornton
• Cyber Threat Trees for Large System Threat Cataloging and Analysis*
• An Axiomatic Analysis Approach for Large-Scale Disaster-Tolerant Systems Modeling
• On the Data Structure Metrics of Quantum Multiple-valued Decision Diagrams David Y. Feinstein and Mitchell A. Thornton D. Michael Miller
• DISASTER TOLERANT SYSTEMS ENGINEERING FOR CRITICAL INFRASTRUCTURE PROTECTION
• QMDD and Spectral Transformation of Binary and Multiple-Valued Functions*
• SECURING UNFAMILAR SYSTEM ENTRY POINTS AGAINST FAULTY USER AUTHENTICATION VIA
• DESIGN AND VALIDATION OF QUATERNARY ARITHMETIC CIRCUITS Approved by
• An Undergraduate Course in Perl: An All Purpose Programming Jason Moore, Mitchell A. Thornton Ronald W. Skeith
• Integrated Design Validation: Combining Simulation and Formal Verification for Digital Integrated Circuits
• Using Multiple-Valued Logic Decision Diagrams to Model System Threat Probabilities
• A Standard Cell Implementation of a Phased Logic CPU Robert B. Reese
• A Coarse-Grain Phased Logic CPU Robert B. Reese Mitchell A. Thornton Cherrice Traver
• Efficient Adder Circuits Based on a Conservative Reversible Logic Gate J.W. Bruce, M.A. Thornton, L. Shivakumaraiah, P.S. Kokate, and X. Li
• G n\Gamma1 0 G n\Gamma1 G n\Gamma1
• Variable Reordering for Shared Binary Decision Diagrams Using Output Probabilities \Lambda
• Tradeoff Analysis of Integer Multiplier Circuits Implemented in FPGAs M. A. Thornton
• Efficient Spectral Coefficient Calculation Using Circuit Output Probabilities
• * supported in part by the Semiconductor Research Corporation under contract 1399 ** supported in part by a Discovery Grant from the Natural Sciences and Engineering Research Council of Canada.
• Components of Disaster Tolerant Computing Chad M. LAWLER
• Advances in Quantum Computing Fault Tolerance and Testing David Y. Feinstein, V.S.S. Nair, and Mitchell A. Thornton
• SBDD Variable Reordering Based on Probabilistic and Evolutionary Algorithms \Lambda
• SPECTRAL BASED NUMERICAL METHODS FOR COMBINATIONAL LOGIC SYNTHESIS
• Odd/Even Cube Covering for Minimizing ESOP Circuits M. A. Thornton B. Q. Vu R. Drechsler
• Cache Resident Data Locality Analysis Q. G. Samdani M. A. Thornton
• INTRODUCTION 1.0 Motivation
• SystemVerilog encapsulates both design description and verification properties in one language and provides
• A QUANTUM CIRCUIT SIMULATOR BASED ON DECISION DIAGRAMS
• Direct Reed-Muller Transform of Digital Logic Netlists Mitchell A. Thornton and Jennifer Dworak
• An Iterative Combinational Logic Synthesis Technique Using Spectral Information
• SWITCHING ACTIVITY ESTIMATION OF FINITE STATE MACHINES FOR LOW POWER SYNTHESIS
• Assessment Analysis in Criteria 2000 M. A. Thornton R. W. Skeith
• Additive bit-serial algorithm for discrete logarithm modulo 2k
• A method for computing the Disjoint-Sum-Of-Products (DSOP) form of Boolean functions is described. The algorithm exploits
• A Low Power Radix-4 Dual Recoded Integer Squaring Implementation For Use in Design of Application Specific Arithmetic Circuits
• Multiple Valued Logic: Concepts and Representations
• Logic Synthesis Based on the Structure of an Ordered DD * M. A. Thornton, D. M. Wessels
• Integration of CAD Tools and Structured Design Principles in an Undergraduate Computer Engineering Curriculum
• Fast and Efficient Equivalence Checking based on NANDBDDs Rolf Drechsler Mitch Thornton
• An Axiomatic Analysis Approach for Large-Scale Disaster-Tolerant Systems Theodore W. MANIKAS, Laura L. SPENNER, Paul D. KRIER,
• Axiomatic Design in the Biomedical Industry Diana EASTON
• Abstract--State space traversal algorithms for Finite State Machine (FSM) models of synchronous sequential circuitry are
• AN AUTOMATED TOOL FOR HDL AND CONFIGURATION FILE GENERATION FROM UML SYSTEM DESCRIPTIONS
• Abstract--A logic style known as Phased Logic(PL) is applied to arithmetic circuits. Phased logic is a dual-rail LEDR logic
• Abstract--The Karhunen-Love spectrum of a discrete function can vary depending on how
• A NOVEL APPROACH TO BUSINESS PROCESS DESIGN IN A REGULATED INDUSTRY
• A GLOBAL MULTIPLE-VALUED CLOCK APPROACH FOR HIGH-PERFORMANCE MULTI-PHASE CLOCK INTEGRATED CIRCUITS
• Computer Engineering Review Task Force Report John Impagliazzo (Moderator) Susan Conry Eric Durant
• Abstract Some high performance digital integrated circuits use multi-phase clock distribution systems with
• *This work was supported in part by US National Science Foundation (NSF) grant CCF-1116405.
• Faculty and Student Perceptions of Online Learning in Engineering Education
• Uncle An RTL Approach to Asynchronous Design Abstract--Uncle (Unified NULL Convention Logic Environment)
• Modeling Medical System Threats with Conditional Probabilities using Multiple-Valued Logic Decision