- Exploiting OnChip Inductance in High Speed Clock Distribution Networks
- Effects of Inductance on the Propagation Delay and Repeater Insertion in VLSI Circuits
- Inductance Effects in RLC Trees Yehea I. Ismail, Eby G. Friedman, and Jose L. Neves 1
- Repeater Insertion in Tree Structured Inductive Interconnect
- Optimum Repeater Insertion Based on a CMOS Delay Model for OnChip RLC Interconnect
- Equivalent Elmore Delay for RLC Trees Yehea I. Ismail, Eby G. Friedman, and Jose L. Neves 1
- IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS, VOL. 19, NO. 3, MARCH 2011 349 I T IS WITH great pleasure and deep sense of responsibility
- On-Chip Inductance in High-Speed Integrated Circuits Call for Papers
- IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS, VOL. 10, NO. 6, DECEMBER 2002 683 Guest Editorial: Special Issue on On-Chip Inductance
- IEEE TRANSACTIONS ON COMPUTER-AIDED DESIGN OF INTEGRATED CIRCUITS AND SYSTEMS, VOL. 24, NO. 3, MARCH 2005 461 Short Papers_______________________________________________________________________________
- 1348 IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS, VOL. 12, NO. 12, DECEMBER 2004 Utilizing the Effect of Relative Delay on Energy
- IEEE TRANSACTIONS ON COMPUTER-AIDED DESIGN OF INTEGRATED CIRCUITS AND SYSTEMS, VOL. 24, NO. 2, FEBRUARY 2005 271 Realizable Reduction of Interconnect Circuits Including
- IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS, VOL. 12, NO. 4, APRIL 2004 437 Modeling Skin and Proximity Effects With Reduced
- 900 IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS, VOL. 11, NO. 5, OCTOBER 2003 Improved Model-Order Reduction by Using Spacial
- IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS, VOL. 10, NO. 6, DECEMBER 2002 685 On-Chip Inductance Cons and Pros
- IEEE2004 CUSTOMINTEGRATEDCIRCUITSCONFERENCE Analysis of Coupling Noise and it's Scalabilityin Dynamic Circuits
- Possible Noise Failure Modes in Static and Dynamic Circuits Masud H. Chowdhury and Yehea I. Ismail
- Optimum Positioning Of Interleaved Repeaters In Bidirectional Buses
- Modeling Skin Effect With Reduced Decoupled R-L Circuits S.Mei and Y. 1.Ismail
- Accurate Rise Time and Overshoots Estimation in RLC Interconnects
- Efficient Model Order Reduction Including Skin Effect Shizhong Mei
- Optimum Repeater InsertionBased on a CMOSDelay Model for On-ChipRLC Interconnect
- On the Extraction of OnChip Inductance Yehea I. Ismail and Eby G. Friedman
- 1264 IEEE TRANSACTIONS ON COMPUTER-AIDED DESIGN OF INTEGRATED CIRCUITS AND SYSTEMS, VOL. 23, NO. 7, JULY 2004 Computation of Signal-Threshold Crossing Times
- Curriculum Vitae Name : Yehea I. Ismail, Fellow IEEE
- Efficient Model Order Reduction via Multi-Node Moment Matching Yehea I. Ismail
- Figures of Merit to Characterize the Importance of OnChip Inductance
- Realizable RLCK Circuit Crunching Chirayu S. Amin Masud H. Chowdhury Yehea I. lsmail
- Fast and Accurate Simulationof Tree StructuredInterconnect' Yehea I. Ismail
