- Comparison of Parallelization Frameworks for Shared Memory Multi-Core Architectures
- FSM-Controlled Architectures for Linear Invasion Farhadur Arifin, Richard Membarth, Abdulazim Amouri, Frank Hannig, and Jurgen Teich
- Model-Based Synthesis and Optimization of Static Multi-Rate Image Processing Algorithms
- A Generalized Static Data Flow Clustering Algorithm for MPSoC Scheduling of Multimedia Applications
- Frameworks for GPU Accelerators: A Comprehensive Evaluation using
- Acceleration of Multiresolution Imaging Algorithms: A Comparative Study
- Discourse on Extending Embedded Medical Image Processing Systems Using the High Speed
- New Directions for FPGA IP Core Watermarking and Identification
- Lifetime Reliability Optimization for Embedded Systems: A System-Level Approach
- System Integration of Tightly-Coupled Reconfigurable Processor Arrays and Evaluation of
- Incorporating Graceful Degradation into Embedded System Design Michael Gla, Martin Lukasiewycz, Christian Haubelt, and Jurgen Teich
- Efficient High-Level Modeling in the Networking Domain Christian Zebelein, Joachim Falk,
- Robust Design of Embedded Systems Martin Lukasiewycz, Michael Gla, and Jurgen Teich
- A Rapid Prototyping System for Error-Resilient Multi-Processor Systems-on-Chip
- A Bus-based SoC Architecture for Flexible Module Placement on Reconfigurable FPGAs
- Efficient Approximately-Timed Performance Modeling for Architectural Exploration of MPSoCs
- Echtzeitanalyse Ethernet-basierter E/E-Architekturen im Felix Reimann
- Adaptive Traffic Scheduling Techniques for Mixed Real-Time and Streaming Applications on
- Maintaining Virtual Areas on FPGAs using Strip Packing with Delays
- Interprocedural Placement-Aware Configuration Prefetching for FPGA-based Systems
- Efficient Mapping of Streaming Applications for Image Processing on Graphics Cards
- Dynamic Decentralized Mapping of Tree-Structured Applications on NoC Architectures
- DynOAA -Dynamic Offset Adaptation Algorithm for Improving Response Times of CAN Systems
- Control Performance-Aware System Level Design Nina Muhleis, Michael Gla, and Jurgen Teich
- Detector Defect Correction of Medical Images on Graphics Processors
- Robustness Analysis of Watermark Verification Techniques for FPGA Netlist Cores
- A System-Level Synthesis Approach from Formal Application Models to Generic Bus-Based MPSoCs
- Multiplexing Methods for Power Watermarking Daniel Ziener, Florian Baueregger, and Jurgen Teich
- Towards Scalable System-Level Reliability Analysis Michael Gla, Martin Lukasiewycz, Christian Haubelt, and Jrgen Teich
- A Self-organizing Distributed Reinforcement Learning Algorithm to Achieve Fair Bandwidth Allocation for Priority-based Bus Communication
- Using the Power Side Channel of FPGAs for Communication
- Electromagnetic Compatibility (EMC) of CAN+* Tobias Ziermann and Jrgen Teich, Hardware/Software Co-Design, Department of Computer Science,
- Exploiting Data-Redundancy in Reliability-Aware Networked Embedded System Design
- FlexRay Schedule Optimization of the Static Segment Martin Lukasiewycz, Michael Gla, and
- Self-organizing Bandwidth Sharing in Priority-based Medium Access Stefan Wildermann, Tobias Ziermann, Jurgen Teich
- SELF-ORGANIZING MULTI-CUE FUSION FOR FPGA-BASED EMBEDDED IMAGING Stefan Wildermann, Gregor Walla, Tobias Ziermann, Jurgen Teich
- Designing Heterogeneous ECU Networks via Compact Architecture Encoding and Hybrid Timing Analysis
- 256 Int. J. Autonomous and Adaptive Communications Systems, Vol. 2, No. 3, 2009 Copyright 2009 Inderscience Enterprises Ltd.
- Designing for Embedded Parallel Computing Platforms: Architectures, Design Tools, and Applications Design, Automation & Test in Europe, April, 2009 -Nice, France
- CAN+: A new backward-compatible Controller Area Network (CAN) protocol with up to 16x higher data rates
- Combined System Synthesis and Communication Architecture Exploration Martin Lukasiewycz, Martin Streubuhr, Michael Gla, Christian Haubelt, and Jurgen Teich
- A Communication Architecture for Complex Runtime Reconfigurable Systems and its Implementation on
- From Model-based Design to Virtual Prototypes for Automotive Applications
- System Level Performance Simulation for Heterogeneous Multi-Processor Architectures
- Netlist-Level IP Protection by Watermarking for LUT-Based FPGAs Moritz Schmid, Daniel Ziener and Jurgen Teich
- Symbolic Voter Placement for Dependability-Aware System Synthesis
- Optimization Flow for Algorithm Mapping on Graphics Cards
- Symbolic System Level Reliability Analysis Michael Gla, Martin Lukasiewycz, Felix Reimann, Christian Haubelt, and Jurgen Teich
- Frameworks for Multi-core Architectures: A Comprehensive Evaluation using
- Efficient Mapping of Multiresolution Image Filtering Algorithms on Graphics Processors
- Run time Mapping of Adaptive Applications onto Homogeneous NoC-based Reconfigurable
- Generating GPU Code from a High-level Representation for Image Processing Kernels
- Analysis of SystemC Actor Networks for Efficient Submitted to the Special issue on
- A Rule-Based Static Dataflow Clustering Algorithm for Efficient Embedded Software Synthesis
- This is the author's version of the work. The definitive work was published in GMM-Fachbericht 69 -Automotive meets Electronics (AmE 2011), pp. 10 -15, 2011. This work was supported in part by the German Federal Ministry of Education and Research (BMBF) u
- Distributed Resource Reservation in Massively Parallel Processor Arrays
- A FLEXIBLE SMART CAMERA SYSTEM BASED ON A PARTIALLY RECONFIGURABLE DYNAMIC FPGA-SOC
- Verifying the Authorship of Embedded IP Cores: Watermarking and Core Identification Techniques
- Decentralized Dynamic Resource Management Support for Massively Parallel Processor Arrays
- ESL POWER AND PERFORMANCE ESTIMATION FOR HETEROGENEOUS MPSOCS USING SYSTEMC
- A Co-Simulation Approach for Control Performance Analysis during Design Space Exploration of
- Dynamic Task-Scheduling and Resource Management for GPU Accelerators in Medical Imaging
