Al-Asaad, Hussain - Department of Electrical and Computer Engineering, University of California, Davis

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Al-Asaad, Hussain - Department of Electrical and Computer Engineering, University of California, Davis

UC Davis 1 Hussain Al-Asaad CURRICULUM VITAE
A New Statistical Approach for Glitch Estimation in Combinational Circuits
On The Design of Fault Tolerant VLSI and WSI Non-Homogenous Multipipelines
LIFETIME VALIDATION OF DIGITAL SYSTEMS VIA FAULT MODELING AND TEST GENERATION
High-Level Design Verification of Microprocessors via Error Modeling
Abstract--Fault collapsing is the process of reducing the number of faults by using redundance and equiva-
1. This research is supported by DARPA under Contract No. DABT63-96-C-0074. The results presented herein do not neces-
Abstract--We present a Mutation-based Validation Paradigm (MVP) technology that can handle complete high-level
A New Method for Power Estimation and Optimization of Combinational Circuits
Our mutation based validation paradigm (MVP) is a validation environment for high-level microprocessor
Abstract--A mutation-based validation paradigm that can han-dle complete high-level microprocessor implementations is pre-
ESIM is a simulation tool that integrates logic fault and design error simulation for logic circuits. It targets several
Microprocessors are becoming increasingly complex and difficult to debug. Researchers are constantly looking
Fault collapsing is the process of reducing the number of faults by using redundance and equivalence/dominance
ABSTRACT--Low power flip-flops are crucial for the design of low-power digital systems. In this paper we delve into the details of
Abstract --With operational faults becoming the dominant cause of failure modes in modern
Exact global fault collapsing can be easily applied locally at the logic gates, however, it is often ignored for large cir-
Abstract--On-line testing is fast becoming a basic fea-ture of digital systems, not only for critical applica-
MUTATION-BASED VALIDATION OF HIGH-LEVEL MICROPROCESSOR IMPLEMENTATIONS
1. This research was supported by General Motors R&D Center. Digest of Papers: IEEE International On-Line Testing Workshop, 1996, pp. 164-167.
MODELING AND DETECTING CONTROL ERRORS IN MICROPROCESSORS
To generate tests for a digital circuit, the test generation tool is initially provided with the circuit description in a
OCTOBERDECEMBER 1998 0740-7475/98/$10.00 1998 IEEE 17 EMBEDDED SYSTEMS are computers in-
Abstract--Our Mutation-based Validation Paradigm (MVP) is a validation environment for high-level microprocessor imple-
CONCURRENT DESIGN ERROR SIMULATION FOR HIGH-LEVEL MICROPROCESSOR IMPLEMENTATIONS
This paper introduces two new methods for observing and recording the vectors that have been asserted on a bus.
LOGIC DESIGN VALIDATION VIA SIMULATION AND AUTOMATIC TEST PATTERN GENERATION1
Functional verification plays a key role in the design verification cycle and the physical fault testing process.
SCALABLE TEST GENERATORS FOR HIGH-SPEED DATAPATH CIRCUITS
A novel Markov model for the reliability prediction of fault-tolerant non-homogenous VLSI and WSI multipipe-
Fault tolerance is often considered as a good additional feature for multiprocessor systems but nowadays it is
Distributed Reconfiguration of Fault Tolerant VLSI Multipipeline Arrays with Constant Interstage Path Lengths
Abstract--We survey a set of flip-flops designed for low power and high performance. We highlight the basic fea-
In this paper, we survey various designs of low-power full-adder cells from conventional CMOS to really inven-