- 1304 TRANSACTIONS COMPUTERAIDED DESIGN INTEGRATED CIRCUITS SYSTEMS, VOL. NOVEMBER Optimal Partitioners and EndCase Placers for
- Overcoming Resolution-Based Lower Bounds for SAT Solvers DoRon B. Motter and Igor L. Markov
- 2002 Fadi A. Aloul, University of Michigan PBS: A Pseudo-Boolean Solver
- Accurate Reliability Evaluation and Enhancement via Probabilistic Transfer Matrices
- To appear in IEEE Trans. on Computer-Aided Design of Integrated Circuits and Systems Min-Cut Floorplacement
- Symmetry and Satisfiability: An Update Hadi Katebi, Karem A. Sakallah, and Igor L. Markov
- To appear in IEEE Transactions on CAD 2008 High-performance Routing at the Nanometer Scale
- Dynamic Symmetry-Breaking for Improved Boolean Optimization Arathi Ramani
- Reversible Logic Circuit Synthesis Vivek V. Shende, Aditya K. Prasad, Igor L. Markov, and John P. Hayes
- Consistent Placement of Macro-Blocks Using Floorplanning and Standard-Cell Placement
- Extended Abstract: Circuit CAD Tools as a Security Threat
- Partitioning With Terminals: A ``New'' Problem and New Benchmarks \Lambda C. J. Alpert + , A. E. Caldwell, A. B. Kahng and I. L. Markov
- GTX: The MARCO GSRC Technology Extrapolation System
- Design and Implementation of the FiducciaMattheyses Heuristic
- Uniformly-switching Logic for Cryptographic Hardware Igor L. Markov Dmitri Maslov
- CONTANGO: Integrated Optimization of SoC Clock Networks Dongjin Lee, Igor L. Markov
- Constraint-Driven Floorplan RepairConstraint-Driven Floorplan Repair Michael D. Moffitt Artificial Intelligence Laboratory (speaker)
- Quadratic Placement Revisited 1 C. J. Alpert, T. Chan, D. J.-H. Huang, I. Markov and K. Yan
- 1120 IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS, VOL. 11, NO. 6, DECEMBER 2003 Fixed-Outline Floorplanning: Enabling
- Optimization LargeScale
- Can Recursive Bisection Alone Produce Routable Placements? Andrew E. Caldwell, Andrew B. Kahng and Igor L. Markov
- Data Structures and Algorithms for Simplifying Reversible Circuits
- OnOn--chip Test Generationchip Test Generation Using Linear SubspacesUsing Linear Subspaces
- Hierarchical Whitespace Allocation in Topdown Placement
- Analytical Engines Are Unnecessary in TopDown PartitioningBased Placement \Lambda
- Sidewinder -A Scalable ILP-Based Router Jin Hu, Jarrod A. Roy, and Igor L. Markov
- Benchmarking For Large-scale Placement and Beyond Saurabh N. Adya, Mehmet C. Yildiz, Igor L. Markov,
- Improving Gate-Level Simulation of Quantum Circuits1 George F. Viamontes,2
- Implementation FiducciaMattheyses
- Enhancing Design Robustness with Reliability-aware Resynthesis and Logic Simulation
- A Compressed Breadth-First Search for Satisfiability DoRon B. Motter and Igor L. Markov
- This paper describes a new algorithm for extracting unsatis-fiable subformulas from a given unsatisfiable CNF formula.
- Watermarking Techniques for Intellectual Property Protection A. B. Kahng, J. Lach, W. H. Mangione-Smith, S. Mantik, I. L. Markov,
- GATE-LEVEL SIMULATION OF QUANTUM CIRCUITS GEORGE F. VIAMONTES, MANOJ RAJAGOPALAN,
- Watermarking Techniques for Intellectual Property Protection \Lambda A. B. Kahng, J. Lach + , W. H. MangioneSmith + , S. Mantik, I. L. Markov,
- Combining Two Local Search Approaches to Hypergraph Partitioning Arathi Ramani and Igor Markov
- Simulation-based Bug Trace Minimization with BMC-based Refinement
- Automatically Exploiting Symmetries in Constraint Programming Arathi Ramani and Igor L. Markov
- Can Recursive Bisection Alone Produce Routable Placements?
- Protecting Bus-based Hardware IP by Secret Sharing Jarrod A. Roy, Farinaz Koushanfar and Igor L. Markov
- 8uh...yr+ 6yfr...## D7H 6+#v Sr+rh...pu Ghi U'' 8uh# V8G6 Hh#urh#vp+ 9rfh...#r# 9rv+ Cht# V8G6 8'f#r... Tpvrpr#T''f+'+ Dt'... Hh...x'o/oo# V8G6 Hh#urh#vp+ 9rfh...#r# Frr#u `h# V8G6 8'f#r... Tpvrpr Qh...#vhyy' +ff'...#rq i' h t...h# s...' 8hqr
- MINIMIZATION Mathematics
- Laboratory, Implications
- Design and implementation of movebased partitioners Andrew Caldwell, Andrew Kahng and Igor Markov
- Improved Algorithms for Hypergraph Bipartitioning Andrew E. Caldwell, Andrew B. Kahng and Igor L. Markov \Lambda
- Improved Algorithms for Hypergraph Bipartitioning
- Node Mergers in the Presence of Don't Cares
- Fast Equivalence-checking for Quantum Circuits Shigeru Yamashita
- Automating Post-Silicon Debugging and Repair Kai-hui Chang, Igor L. Markov, Valeria Bertacco
- Solving Difficult SAT Instances in the Presence of Symmetry Fadi A. Aloul, Arathi Ramani, Igor L. Markov and Karem A. Sakallah
- ome researchers suggest achieving mas-sive speedups in computing by exploiting
- Smaller Two-Qubit Circuits for Quantum Communication and Computation Vivek V. Shende
- Reversible Logic Circuit Synthesis Vivek V. Shende, Aditya K. Prasad, Igor L. Markov, and John P. Hayes
- An Introduction to Reversible Circuits Igor L. Markov, The University of Michigan
- Seeing the Forest and the Trees: Steiner Wirelength
- Relaxed Partitioning Balance Constraints in TopDown Placement \Lambda Andrew E. Caldwell, Andrew B. Kahng and Igor L. Markov
- SPECIAL ISSUE FOR SYSTEM LEVEL INTERCONNECT PREDICTION (SLIP) GUEST EDITORS: DENNIS SYLVESTER AND ANDREW KAHNG 1 Error-Correction and Crosstalk Avoidance in DSM Busses
- Optimal End-Case Partitioners and Placers for Standard-Cell Layout A. E. Caldwell, A. B. Kahng and I. L. Markov
- Completing High-quality Global Routes University of Michigan
- GTX: The MARCO GSRC Technology Extrapolation System
- On Wirelength Estimations for RowBased Placement \Lambda Andrew E. Caldwell, Andrew B. Kahng, Stefanus Mantik, Igor L. Markov and Alex Zelikovsky
- Hypergraph Partitioning for VLSI CAD: Methodology for Heuristic Development, Experimentation and Reporting \Lambda
- Can Recursive Bisection Alone Produce Routable Placements?
- Synthesis of Quantum Logic Circuits Vivek V. Shende1 Stephen S. Bullock2 Igor L. Markov1
- Low-power Clock Trees for CPUs Dong-Jin Lee, Myung-Chul Kim and Igor L. Markov
- MINCE: A Static Global Variable-Ordering Heuristic for SAT Search and BDD Manipulation
- Post-Placement Rewiring and Rebuffering by Exhaustive Search for Functional Symmetries
- Improving Testability and Soft-Error Resilience through Retiming Smita Krishnaswamy , Igor L. Markov , John P. Hayes
- Solving Hard Instances of Floorplacement Aaron Ng, Igor L. Markov
- Analytical Minimization of Half-Perimeter Wirelength Andrew Kennings and Igor Markov
- 1/24/2007 1 ECO-system: Embracing
- On-Chip Test Generation Using Linear Subspaces Ramashis Das, Igor L. Markov, John P. Hayes
- Fast Simulation and Equivalence Checking using O p enA ccess
- Fixedoutline Floorplanning Through Better Local Search Saurabh N. Adya and Igor L. Markov
- When are Multiple Gate Errors Significant in Logic Smita Krishnaswamy, Igor L. Markov, John P. Hayes
- Partitioners StandardCell
- Smoothening Max-terms and Analytical Minimization of Half-Perimeter Wirelength
- Optimal Synthesis of Linear Reversible Circuits Ketan N. Patel, Igor L. Markov and John P. Hayes
- CONTANGO: Integrated Optimization of SoC Clock Networks Dongjin Lee and Igor L. Markov
- IPWatermarking Methodologies
- PartitioningWith {caldwell,abk,imarkov}@cs.ucla.edu alpert@austin.ibm.com April
- Function Smoothing with Applications to VLSI Layout \Lambda Ross Baldick 1 , Andrew B. Kahng 2 , Andrew Kennings 3 and Igor L. Markov 4
- Fast Simulation and Equivalence Checking Using OAGear Kai-hui Chang, David A. Papa, Igor L. Markov and Valeria Bertacco
- Overcoming ResolutionOvercoming Resolution--BasedBased Lower Bounds for SAT SolversLower Bounds for SAT Solvers
- Seeing the Forest and the Trees: Steiner Wirelength Optimization in Placement
- Practical Slicing and Non-slicing Block-Packing without Simulated Annealing
- On Proof Systems Behind Efficient SAT Solvers
- Optimizing Non-Monotonic Interconnect using Functional Simulation and Logic Restructuring
- Combinatorial Techniques for Mixed-size S. N. Adya and I. L. Markov
- SafeResynth: A New Technique for Physical Synthesis Kai-hui Chang, Igor L. Markov and Valeria Bertacco
- OPTIMAL PARTITIONERS AND END-CASE PLACERS FOR STANDARD-CELL LAYOUT A. E. Caldwell, A. B. Kahng and I. L. Markov
- Fixed-outline Floorplanning Through Better Local Search Saurabh N. Adya and Igor L. Markov
- AnSER: A Lightweight Reliability Evaluator for use in Logic Synthesis
- IMPLICATIONS OF AREAARRAY I/O FOR ROWBASED PLACEMENT METHODOLOGY \Lambda
- Hypergraph Partitioning for VLSI CAD: Methodology for Heuristic Development, Experimentation and Reporting
- Constraint-Driven Floorplan Repair MICHAEL D. MOFFITT
- OPTIMAL PARTITIONERS AND ENDCASE PLACERS FOR STANDARDCELL LAYOUT \Lambda A. E. Caldwell, A. B. Kahng and I. L. Markov
- Analytical Placement of Hypergraphs ---I Andrew Kennings and Igor Markov
- Almost-symmetries of Graphs Igor L. Markov
- On Wirelength Estimations for Row-Based Placement Andrew E. Caldwell, Andrew B. Kahng, Stefanus Mantik, Igor L. Markov and Alex Zelikovsky
- On Whitespace and Stability in Physical Synthesis Saurabh N. Adya, Igor L. Markov , Paul G. Villarrubia
- ECO-system: Embracing the Change in Placement Jarrod A. Roy and Igor L. Markov
- Utility of the OpenAccess Database in Academic Research David. A. Papa
- A Compressed BreadthFirst Search for Satisfiability DoRon B. Motter and Igor L. Markov
- Consistent Placement of MacroBlocks Using Floorplanning and StandardCell Placement
- Symmetry-Breaking for Pseudo-Boolean Formulas Fadi A. Aloula,b, Arathi Ramania, Igor L. Markova, Karem A. Sakallaha
- Accepted to ICCAD '02 Optimized solvers for the Boolean Satisfiability (SAT) prob-
- Quantum Information and Computation, Vol. 5, No. 2 (2005) 113130 c Rinton Press
- Constructive Benchmarking for Placement David. A. Papa
- Practical Slicing and Non-slicing Block-Packing without Simulated Annealing
- On the Decreasing Significance of Large Standard Cells in Technology Mapping
- Solving Difficult Instances of Boolean Satisfiability in the Presence of Symmetry
- Min-Max Placement For Large-Scale Timing Optimization Andrew B. Kahng , Stefanus Mantik and Igor L. Markov
- Synthesis of Quantum Logic Circuits Vivek V. Shende1
- Restoring Circuit Structure From
- Reversible Logic Circuit Synthesis Vivek V. Shende, Aditya K. Prasad, Igor L. Markov, and John P. Hayes
- Overcoming ResolutionBased Lower Bounds for SAT Solvers DoRon B. Motter and Igor L. Markov
- Faster SAT and Smaller BDDs via Common Function Structure
- Many important tasks in circuit design and verification can be per-formed in practice via reductions to Boolean Satisfiability (SAT), mak-
- EPIC: Ending Piracy of Integrated Circuits Jarrod A. Roy, Farinaz Koushanfar and Igor L. Markov
- High-performance Routing at the Nanometer Scale Jarrod A. Roy and Igor L. Markov
- CONSTRAINTS PARTITIONING
- Analytical Optimization Of Signal Delays in VLSI Placement Andrew B. Kahng ] and Igor L. Markov #
- Hypergraph Partitioning With Fixed Vertices \Lambda Andrew E. Caldwell, Andrew B. Kahng and Igor L. Markov
- Enhancing Design Robustness with Reliability-aware Resynthesis and Logic Simulation
- Toward a Software Architecture for Quantum Computing Design Tools
- 1304 IEEE TRANSACTIONS ON COMPUTER-AIDED DESIGN OF INTEGRATED CIRCUITS AND SYSTEMS, VOL. 19, NO. 11, NOVEMBER 2000 Optimal Partitioners and End-Case Placers for
- Error-Correction and Crosstalk Avoidance in DSM Busses Ketan N. Patel and Igor L. Markov
- Satisfying Whitespace Requirements in Top-down Placement
- Robust IP Watermarking Methodologies for Physical Design Andrew B. Kahng, Stefanus Mantik, Igor L. Markov, Miodrag Potkonjak,
- Topic category: "Error Trace Interpretation & Debugging" Automatic Error Diagnosis and Correction for RTL Designs
- Can Recursive Bisection Alone Produce Routable Placements? \Lambda Andrew E. Caldwell, Andrew B. Kahng and Igor L. Markov
- MinMax Placement For LargeScale Timing Optimization Andrew B. Kahng ] , Stefanus Mantik + and Igor L. Markov #
- Robust IP Watermarking Methodologies for Physical Design \Lambda Andrew B. Kahng, Stefanus Mantik, Igor L. Markov, Miodrag Potkonjak,
- Partitioning-based Methods for VLSI Placement Jarrod A. Roy and Igor L. Markov
- Capo: Robust and Scalable Open-Source Min-Cut Floorplacer Jarrod A. Roy, David A. Papa, Saurabh N. Adya*,
- Unification of Partitioning, Placement and Floorplanning Saurabh N. Adya
- Scalable Simplification of Reversible Circuits Vivek V. Shende, Aditya K. Prasad, Ketan N. Patel, Igor L. Markov and John P. Hayes
- A Compressed Breadth-First Search for Satisfiability
- Partitioning With Terminals: A "New" Problem and New Benchmarks C. J. Alpert, A. E. Caldwell, A. B. Kahng and I. L. Markov
- Early Research Experience With OpenAccess Gear: An Open Source Development Environment
- GTX: The MARCO GSRC Technology Extrapolation System \Lambda http://vlsicad.cs.ucla.edu/GSRC/GTX/
- Analytical Minimization of HalfPerimeter Wirelength Andrew Kennings and Igor Markov \Lambda
- Hypergraph Partitioning and Clustering David A. Papa and Igor L. Markov
- FASTER MINIMIZATION OF LINEAR WIRELENGTH FOR GLOBAL PLACEMENT
- 2011. XI, 310 p. 150 illus. Hardcover SFr. 86.00
- >springer.com ViamontesMarkovHayesQuantumCircuitSimulation
- Large-scale Boolean Matching Hadi Katebi and Igor L. Markov
- Capo: Congestion-driven Placement for Standard-cell and RTL Netlists with Incremental Capability
- Automatically Exploiting Symmetries in Constraint Programming
- Design and Implementation of the Fiduccia-Mattheyses Heuristic
- Logic Synthesis and Circuit Customization Using Extensive External Don't-Cares
- InVerS: An Incremental Verification System with Circuit-Similarity Metrics and Error Visualization
- Signature-based SER Analysis and Design of Logic Circuits Smita Krishnaswamy , Stephen M. Plaza , Igor L. Markov , and John P. Hayes
- RUMBLE: An Incremental, Timing-driven, Physical-synthesis Optimization Algorithm
- Fixing Design Errors with Counterexamples and Resynthesis
- ECO-system: Embracing the Change in Placement
- Tracking Uncertainty with Probabilistic Logic
- Journal of Artificial Intelligence Research 26 (2006) 191-224 Submitted 10/04; published 07/06 Breaking Instance-Independent Symmetries
- C O V E R F E A T U R E 0018-9162/06/$20.00 2006 IEEE74 Computer Published by the IEEE Computer Society
- Resolution Cannot Polynomially Simulate Compressed-BFS
- Fault Testing for Reversible Circuits Ketan N. Patel, John P. Hayes and Igor L. Markov
- Minimal Universal Two-Qubit CNOT-based Circuits Vivek V. Shende1 Igor L. Markov2 Stephen S. Bullock3
- IEEE TRANSACTIONS ON COMPUTER-AIDED DESIGN OF INTEGRATED CIRCUITS AND SYSTEMS, VOL. 22, NO. 11, NOVEMBER 2003 1 Hierarchical Whitespace Allocation in
- Arbitrary two-qubit computation in 23 elementary gates Stephen S. Bullock*
- Improved A Priori Interconnect Predictions and Technology Extrapolation in the GTX System
- ACCELERATING CHANGES in process tech-nology, system implementation platforms, and
- Obstacle-aware Clock-tree Shaping during Placement Dong-Jin Lee
- Assembling 2D Blocks into 3D Chips Johann Knechtel
- Spinto: High-performance Energy Minimization in Spin Glasses
- Abstract--We propose a methodology for Boolean matching under permutations of inputs and outputs (PP-equivalence checking
- CRISP: Congestion Reduction by Iterated Spreading during Placement
- On the Role of Timing Masking in Reliable Logic Circuit Design Smita Krishnaswamy , Igor L. Markov , and John P. Hayes
- Special Session 3B New Topic: Why Nanoscale Physics Favors Quantum Information &
- The Coming of Age of (Academic) Global Routing [Invited Paper]
- RUMBLE: An Incremental, Timing-driven, Physical-synthesis Optimization Algorithm
- Checking Equivalence of Quantum Circuits and States George F. Viamontes, Igor L. Markov, and John P. Hayes
- Critical path in a placement Design: DES
- Node Mergers in the Presence of Don't Cares Stephen M. Plaza, Kai-hui Chang, Igor L. Markov, Valeria Bertacco
- Pre-silicon Post-silicon *Manual functional error correction
- AlmostAlmost--Symmetries of GraphsSymmetries of Graphs Igor Markov, University of MichiganIgor Markov, University of Michigan
- Constraint-Driven Floorplan Repair Michael D. Moffitt
- Seeing the Forest and the Trees: Steiner Wirelength Optimization in Placement
- Solving Hard Instances of Floorplacement
- Are Floorplan Representations Important In Digital Design?
- Toward Quality EDA Tools and Tool Flows Through High-Performance Computing
- Exploiting Structure in Symmetry Detection for CNF Paul T. Darga, Mark H. Liffiton, Karem A. Sakallah, and Igor L. Markov
- On Legalization of Row-Based Placements Cell overlaps and pin blockages by power stripes in the results
- Graph-based simulation of quantum computation in the density matrix representation
- Boosting: Min-Cut Placement with Improved Signal Delay Andrew B. Kahng
- High-Performance QuIDD-based Simulation of Quantum Circuits George F. Viamontes, Igor L. Markov, and John P. Hayes
- On Whitespace and Stability in Mixed-Size Placement and Physical Synthesis
- Identifying and breaking the symmetries of CNF for-mulae has been shown to lead to significant reductions
- Fault Testing for Reversible Circuits Ketan N. Patel, John P. Hayes and Igor L. Markov
- Gate-Level Simulation of Quantum Circuits George F. Viamontes, Manoj Rajagopalan,
- Solving Difficult SAT Instances In The Presence of Symmetry
- Analytical Optimization Of Signal Delays in VLSI Placement Andrew B. Kahng and Igor L. Markov
- GTX: The MARCO GSRC Technology Extrapolation System http://vlsicad.cs.ucla.edu/GSRC/GTX/
- Improved Algorithms for Hypergraph Bipartitioning Andrew E. Caldwell, Andrew B. Kahng and Igor L. Markov
- Hypergraph Partitioning With Fixed Vertices Andrew E. Caldwell, Andrew B. Kahng and Igor L. Markov
- Function Smoothing with Applications to VLSI Layout Ross Baldick1, Andrew B. Kahng2, Andrew Kennings3 and Igor L. Markov4
- Relaxed Partitioning Balance Constraints in Top-Down Placement Andrew E. Caldwell, Andrew B. Kahng and Igor L. Markov
- IMPLICATIONS OF AREA-ARRAY I O FOR ROW-BASED PLACEMENT METHODOLOGY
- CAD Tool Development for Multi-Million Gate Designs Jarrod A. Roy, David A. Papa, James F. Lu, Aaron N. Ng, Igor L. Markov
- Advanced Computer Architecture Laboratory Synthesis and Gate-Level Simulation
- Post-Placement Rewiring and Rebuffering by Exhaustive Search for Functional Symmetries
- Is Quantum Search Practical? George F. Viamontes, Igor L. Markov, and John P. Hayes
- Is Quantum Search Practical? George F. Viamontes
- Optimal SynthesisOptimal Synthesis of Linear Reversible Circuitsof Linear Reversible Circuits
- Symmetries in Rectangular Block-Packing Hay-Wai Chan1
- Evaluating Circuit Reliability Under Probabilistic Gate-Level Fault Models
- Reversible Logic Circuit SynthesisReversible Logic Circuit Synthesis Vivek V. Shende, Aditya K. Prasad,Vivek V. Shende, Aditya K. Prasad,
- Faster SAT and Smaller BDDs via Common Function Structure
- Design and implementation of move-based partitioners Andrew Caldwell, Andrew Kahng and Igor Markov
- Analytical Placement of Hypergraphs | I Andrew Kennings and Igor Markov
- Hierarchical Whitespace Allocation in Top-down Placement
- On the Costs and Benefits of Stochasticity in Stream Processing Raj R. Nadakuditi and Igor L. Markov, University of Michigan
- Quantum Information and Computation, Vol. 5, No. 1 (2005) 049057 c Rinton Press
- Fast Verification of Retiming Kai-hui Chang, Igor L. Markov and Valeria Bertacco
- Faster Symmetry Discovery using Sparsity of Symmetries Paul T. Darga, Karem A. Sakallah, and Igor L. Markov
- Circuit Placement: 2000-Caldwell,Kahng,Markov; 2002-Kennings,Markov; 2006-Kennings,Vorwerk
- DAC.COM KNOWLEDGE CENTER ARTICLE www.dac.com
- Logic Circuit Testing for Transient Faults Smita Krishnaswamy, Igor L. Markov, and John P. Hayes
- On Sub-optimality and Scalability of Logic Synthesis Tools
- OnWirelength Estimations
- Optimal EndCase Partitioners and Placers for StandardCell Layout A. E. Caldwell, A. B. Kahng and I. L. Markov
- Analytical Minimization of HalfPerimeter Wirelength
- Applications baldick@ece.utexas.edu,
- Post-placement Rewiring by Exhaustive Search for Functional Symmetries
- The MINCE heuristic for variable-ordering [1] successfully reduces the size of BDDs and can accelerate SAT-solving. Applications to
- Solving Difficult SAT Instances In The Presence of Symmetry
- SPIRE: A Retiming-Based Physical-Synthesis Transformation System
- Unification of Partitioning, Placement and Floorplanning
- Fast Equivalence-checking for Quantum Circuits SHIGERU YAMASHITA IGOR L. MARKOV
- Algorithmic Tuning of Clock Trees and Derived Non-Tree Structures
- SimPL: An Effective Placement Algorithm Myung-Chul Kim, Dong-Jin Lee and Igor L. Markov
- Obstacle-aware Clock-tree Shaping during Placement
- IEEE TRANSACTIONS ON COMPUTER-AIDED DESIGN OF INTEGRATED CIRCUITS AND SYSTEMS 1 Assembling 2D Blocks into 3D Chips
- MAPLE: Multilevel Adaptive PLacEment for Mixed-Size Designs Myung-Chul Kim
- Securely Sealing Multi-FPGA Systems Tim Guneysu1
- RTL Analysis and Modifications for Improving At-speed Test
- Conflict Anticipation in the Search for Graph Automorphisms