Koren, Israel - Department of Electrical and Computer Engineering, University of Massachusetts at Amherst

Advanced Search

Koren, Israel - Department of Electrical and Computer Engineering, University of Massachusetts at Amherst

A UNIFIED NEGATIVE BINOMIAL DISTRIBUTION FOR YIELD ANALYSIS OF DEFECT TOLERANT CIRCUITS 1
Layer Reassignment for Antenna Effect Minimization in 3-Layer Channel Routing *
Should Yield be a Design Objective? Israel Koren
"!# "$&%'$&(0)1$2(34$2657 98@)15BAC"%EDGFH)1I SUTWV X`YacbdfeWbhgiacpWqsrutveWpwaxdfX`yQpWdax a d&V pWXdfeWc
Constructive floorplanning with a yield objective Rajnish Prasad and Israel Koren
PROCEEDINGS OF THE IEEE, VOL. 86, NO. 9, SEPTEMBER 1998 1819 Defect Tolerance in VLSI Circuits
Fault Sensitivity Analysis and Reliability Enhancement of Analog-to-Digital Converters
Incorporating Fault Tolerance in Analog-to-Digital Converters (ADCs) Mandeep Singh
Determination of yield bounds prior to routing Arunshankar Venkataraman * and Israel Koren
Yield and Routing Objectives in Floorplanning Israel Koren and Zahava Koren
Analysis of a Hybrid Defect-Tolerance Scheme for High-Density Memory ICs
Crosstalk Minimization in Three-Layer HVH Channel Routing
Techniques for Yield Enhancement of VLSI Adders 1 Zhan Chen and Israel Koren
ON THE EFFECT OF FLOORPLANNING ON THE YIELD OF LARGE AREA INTEGRATED CIRCUITS 1
Reliability Enhancement of Analog-to-Digital Converters Mandeep Singh and Israel Koren
Trade-Offs between Yield and Reliability Enhancement *
Techniques for transient fault sensitivity analysis and reduction in VLSI circuits
A Self-Correcting Active Pixel Camera Israel Koren, Glenn Chapman y and Zahava Koren
The E ect of Placement on Yield for Standard Cell Designs Rajnish K. Prasad and Israel Koren
Advanced Fault-Tolerance Techniques For A Color Digital Camera-On-A-Chip
Determination of yield bounds prior to routing Arunshankar Venkataraman * and Israel Koren
Incorporating Fault Tolerance in AnalogtoDigital Converters (ADCs) Mandeep Singh and Israel Koren
Transient Fault Sensitivity Analysis of AnalogtoDigital Converters (ADCs) Mandeep Singh , Ravinder Rachala and Israel Koren
Appeared in IEEE Transactions on Semiconductor Manufacturing, May 1995 An Interactive VLSI CAD Tool for Yield Estimation \Lambda
Proceedings of the IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems (DFT'00) 0-7695-0719-0/00 $10.00 2000 IEEE
The Effect of Spot Defects on the Parametric Yield of Long Interconnection Lines