Zhou, Hai - Department of Electrical and Computer Engineering, Northwestern University

• Fast Min-Cost Buffer Insertion under Process Variations Ruiming Chen and Hai Zhou
• 1222 IEEE TRANSACTIONS ON COMPUTER-AIDED DESIGN OF INTEGRATED CIRCUITS AND SYSTEMS, VOL. 26, NO. 7, JULY 2007 Tradeoff Between Latch and Flop for Min-Period
• Information Processing Letters 81 (2002) 271276 Efficient minimum spanning tree construction
• A Dynamic-Programming Algorithm for Reducing the Energy Consumption of Pipelined System-Level Streaming Applications
• Address Generation for Nanowire Decoders Jia Wang Ming-Yang Kao Hai Zhou
• 1140 IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS, VOL. 14, NO. 10, OCTOBER 2006 Statistical Timing Yield Optimization by Gate Sizing
• A Flexible Data Structure for Efficient Buffer Insertion Ruiming Chen and Hai Zhou
• Optimal Low Power XOR Gate Decomposition Hai Zhou 1 , D. F. Wong 2
• Advances in Computation of the Maximum of a Set of Random Debjit Sinha, Hai Zhou, and Narendra V. Shenoy
• Clock Schedule Verification Under Process Variations Ruiming Chen and Hai Zhou
• Provably Good and Practically Efficient Algorithms for CMP Chunyang Feng1
• IEEE TRANSACTIONS ON COMPUTER-AIDED DESIGN OF INTEGRATED CIRCUITS AND SYSTEMS, VOL. 22, NO. 9, SEPTEMBER 2003 1261 Timing Analysis With Crosstalk is a
• Trade-off between Latch and Flop for Min-Period Sequential Circuit Designs with Chuan Lin and Hai Zhou
• 1264 IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS, VOL. 14, NO. 11, NOVEMBER 2006 Clustering for Processing Rate Optimization
• Timing Verification with Crosstalk for Transparently Latched Circuits
• An Efficient Buffer Insertion Algorithm for Large Networks Based on Lagrangian Relaxation
• Buffer Minimization in Pass Transistor Logic Advanced Technology Group
• CrosstalkConstrained Maze Routing Based on Lagrangian Relaxation Hai Zhou and D.F. Wong
• Complete-k-Distinguishability for Retiming and Resynthesis Equivalence Checking Without Restricting Synthesis
• IEEE TRANSACTIONS ON COMPUTER-AIDED DESIGN OF INTEGRATED CIRCUITS AND SYSTEMS, VOL. 25, NO. 9, SEPTEMBER 2006 1847 Short Papers
• An Efficient Incremental Algorithm for Min-Area Retiming Jia Wang and Hai Zhou
• 1340 IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS, VOL. 13, NO. 12, DECEMBER 2005 Wire Retiming as Fixpoint Computation
• Retiming and Resynthesis with Sweep Are Complete for Sequential Transformation
• IEEE TRANSACTIONS ON COMPUTER-AIDED DESIGN OF INTEGRATED CIRCUITS AND SYSTEMS, VOL. 26, NO. 3, MARCH 2007 447 Low-Power Optimization by Smart Bit-Width
• Optimal River Routing with Crosstalk Constraints
• IEEE TRANSACTIONS ON COMPUTER-AIDED DESIGN OF INTEGRATED CIRCUITS AND SYSTEMS, VOL. 18, NO. 11, NOVEMBER 1999 1683 [10] M. Reidel and J. Rajski, "Fault coverage analysis of RAM test algo-
• Wire Retiming for System-On-Chip by Fixpoint Computation Chuan Lin and Hai Zhou
• IEEE TRANSACTIONS ON COMPUTER-AIDED DESIGN OF INTEGRATED CIRCUITS AND SYSTEMS, VOL. 25, NO. 9, SEPTEMBER 2006 1577 Optimal Wire Retiming Without Binary Search
• SIGNAL INTEGRITY AND LOW POWER ISSUES IN DEEP SUBMICRON VLSI DESIGN
• An Efficient Current-Based Logic Cell Model for Crosstalk Delay Analysis Debasish Das
• IEEE TRANSACTIONS ON COMPUTER-AIDED DESIGN OF INTEGRATED CIRCUITS AND SYSTEMS, VOL. 20, NO. 5, MAY 2001 693 Buffer Minimization in Pass Transistor Logic
• New Block-Based Statistical Timing Analysis Approaches Without Moment Ruiming Chen and Hai Zhou
• A Timing Dependent Power Estimation Framework Considering Debjit Sinha, DiaaEldin Khalil, Yehea Ismail and Hai Zhou
• 1064 IEEE TRANSACTIONS ON COMPUTER-AIDED DESIGN OF INTEGRATED CIRCUITS AND SYSTEMS, VOL. 25, NO. 6, JUNE 2006 Gate-Size Optimization Under Timing Constraints
• Interconnect Estimation without Packing via ACG Floorplans Jia Wang and Hai Zhou
• 1522 IEEE TRANSACTIONS ON COMPUTER-AIDED DESIGN OF INTEGRATED CIRCUITS AND SYSTEMS, VOL. 26, NO. 8, AUGUST 2007 Advances in Computation of the Maximum of a
• Integrated Floorplanning and Interconnect Planning \Lambda HungMing Chen 1 , Hai Zhou 1y , F.Y. Young 1z , D.F. Wong 1 , Hannah H. Yang 2 , and Naveed Sherwani 2
• A New Efficient Retiming Algorithm Derived by Formal Manipulation Electrical and Computer Engineering
• 3004 IEEE TRANSACTIONS ON COMPUTER-AIDED DESIGN OF INTEGRATED CIRCUITS AND SYSTEMS, VOL. 25, NO. 12, DECEMBER 2006 [12] L. P. Carloni and A. L. Sangiovanni-Vincentelli, "Performance analy-
• An Exact Gate Decomposition Algorithm for LowPower Technology Mapping Hai Zhou and D.F. Wong
• Timing Analysis with Crosstalk as Fixpoints on Complete Lattice
• FA-STAC: A Framework for Fast and Accurate Static Timing Analysis with Coupling
• IEEE TRANSACTIONS ON COMPUTER-AIDED DESIGN OF INTEGRATED CIRCUITS AND SYSTEMS, VOL. 25, NO. 12, DECEMBER 2006 2965 Statistical Timing Analysis With Coupling
• An Efficient System-Level to RTL Verification Framework for Computation-Intensive Applications
• Binning Optimization based on SSTA for Transparently-Latched Circuits
• Processing Rate Optimization by Sequential System Floorplanning Jia Wang Ping-Chih Wu Hai Zhou
• Statistical Reliability Analysis Under Process Variation and Aging Effects
• IEEE TRANSACTIONS ON COMPUTER-AIDED DESIGN OF INTEGRATED CIRCUITS AND SYSTEMS, VOL. 26, NO. 11, NOVEMBER 2007 2069 Short Papers
• Exploring Adjacency in Floorplanning Electrical and Computer Engineering
• Parallel Cross-Layer Optimization of High-Level Synthesis and Physical Design
• How Powerful is Retiming? \Lambda Hai Zhou y Vigyan Singhal z Adnan Aziz x
• Efficient Minimum Spanning Tree Construction without Delaunay Triangulation
• Interconnect-Driven Floorplanning by Searching Alternative Packings Chiu-wing Sham Evangeline F. Y. Young Hai Zhou
• NORTHWESTERN UNIVERSITY Timing Analysis and Optimization Techniques for VLSI Circuits
• NORTHWESTERN UNIVERSITY Timing Optimization Algorithms for Sequential Circuits
• A New Efficient Retiming Algorithm Derived by Formal Manipulation
• Yield Driven Gate Sizing for Coupling-Noise Reduction under Uncertainty
• Formal Methods in System Design, 22, 205224, 2003 c 2003 Kluwer Academic Publishers. Manufactured in The Netherlands.
• Pessimism Reduction in Coupling-Aware Static Timing Analysis Using Timing and Logic Filtering
• iRetILP: An efficient incremental algorithm for min-period retiming under general delay model Debasish Das
• Fast Buffer Insertion for Yield Optimization Under Process Ruiming Chen and Hai Zhou
• Design Closure Driven Delay Relaxation Based on Convex Cost Network Flow Chuan Lin Aiguo Xie Hai Zhou
• A Practical Method for Multi-Domain Clock Skew Optimization
• Leakage Power Optimization With Dual-Vth Library In High-Level Synthesis*
• An Optimal Algorithm for River Routing with Crosstalk Constraints
• Optimal NonUniform WireSizing under the Elmore Delay Model ChungPing Chen, Hai Zhou, and D. F. Wong
• Efficient Steiner Tree Construction Based on Spanning Electrical and Computer Engineering
• Clustering for Processing Rate Optimization Chuan Lin, Jia Wang, and Hai Zhou
• Global Routing with Crosstalk Constraints \Lambda Hai Zhou and D.F. Wong
• Impact of Modern Process Technologies on the Electrical Parameters of Interconnects
• Post-Routing Layer Assignment for Double Patterning , Yinghai Lu2
• Retiming for Synchronous Data Flow Graphs N. Liveris C. Lin J. Wang H. Zhou P. Banerjee
• ACGAdjacent Constraint Graph for General Floorplans Hai Zhou and Jia Wang
• Efficient Algorithms for Buffer Insertion in General Circuits Based on Network Flow
• 1576 IEEE TRANSACTIONS ON COMPUTER-AIDED DESIGN OF INTEGRATED CIRCUITS AND SYSTEMS, VOL. 26, NO. 9, SEPTEMBER 2007 Unified Incremental Physical-Level
• Gate Sizing for Crosstalk Reduction under Timing Constraints by Lagrangian Relaxation
• NORTHWESTERN UNIVERSITY Analysis and Optimization under Crosstalk and Variability in
• NORTHWESTERN UNIVERSITY SystemLevel Optimizations for High Performance DSM Circuits
• 704 IEEE TRANSACTIONS ON COMPUTER-AIDED DESIGN OF INTEGRATED CIRCUITS AND SYSTEMS, VOL. 23, NO. 5, MAY 2004 Efficient Steiner Tree Construction
• 1338 IEEE TRANSACTIONS ON COMPUTER-AIDED DESIGN OF INTEGRATED CIRCUITS AND SYSTEMS, VOL. 23, NO. 9, SEPTEMBER 2004 Retiming for Wire Pipelining in System-On-Chip
• IEEE TRANSACTIONS ON COMPUTER-AIDED DESIGN OF INTEGRATED CIRCUITS AND SYSTEMS, VOL. 26, NO. 8, AUGUST 2007 1445 Optimal Jumper Insertion for Antenna Avoidance
• IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS, VOL. 16, NO. 3, MARCH 2008 241 Fast Estimation of Timing Yield Bounds
• Retiming for Wire Pipelining in System-On-Chip Chuan Lin and Hai Zhou
• Q. Zhu, H. Zhou, T. Jing, X. Hong, Y. Yang Efficient Octilinear Steiner Tree Construction Based on Spanning Graphs
• Minimal Period Retiming Under Process Variations Jia Wang and Hai Zhou
• Timing Macro-modeling of IP Blocks with Crosstalk Ruiming Chen and Hai Zhou
• Optimal Wire Retiming Without Binary Search Chuan Lin and Hai Zhou
• Deriving a New Efficient Algorithm for Min-Period Retiming ECE, Northwestern University, Evanston, IL 60208
• Statistical Gate Sizing for Timing Yield Optimization Debjit Sinha
• A Unified Framework for Statistical Timing Analysis with Coupling and Multiple Input Switching
• Smart Bit-width Allocation for Low Power Optimization in a SystemC based ASIC Design Environment1
• An Efficient Retiming Algorithm Under Setup and Hold Constraints
• Optimal Jumper Insertion for Antenna Avoidance under Ratio Upper-Bound
• Clock Skew Scheduling with Delay Padding for Prescribed Skew Domains Chuan Lin Hai Zhou
• Nostra-XTalk : A Predictive Framework for Accurate Static Timing Analysis in UDSM VLSI Circuits
• Timing Budgeting under Arbitrary Process Variations Ruiming Chen and Hai Zhou
• An O(nlogn) Edge-Based Algorithm for Obstacle-Avoiding Rectilinear Steiner Tree Construction
• Linear Constraint Graph for Floorplan Optimization with Soft Blocks
• Risk Aversion Min-Period Retiming Under Process Variations Electrical and Computer Engineering
• Multicore Parallel Min-Cost Flow Algorithm for CAD Applications
• Hybrid Energy Storage System Integration For Vehicles , Hai Zhou
• Low Power Discrete Voltage Assignment Under Clock Skew , Jian Sun2
• Clock Schedule Verification with Crosstalk Electrical and Computer Engineering
• Gate Sizing by Lagrangian Relaxation Revisited Jia Wang, Debasish Das, and Hai Zhou
• An Efficient Algorithm for Multi-Domain Clock Skew Yanling Zhi1
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