- 2008,KevinSkadron A Short Tutorial on Thermal
- Many-Core Design from a Thermal Perspective , Mircea R. Stan
- Differentiating the Roles of IR Measurement and Simulation for Power and Temperature-Aware Design
- Temperature-to-Power Mapping Zhenyu Qi, Brett H. Meyer, Wei Huang, Robert J. Ribando, Kevin Skadron, Mircea R. Stan
- USING ON-CHIP EVENT COUNTERS FOR HIGH-RESOLUTION, REAL-TIME TEMPERATURE MEASUREMENT1
- ACM Computing Survey, Vol. X, No. X, Article X, Pub. date:. Recent Thermal Management Techniques for
- Graphics Hardware (2006) M. Olano, P. Slusallek (Editors)
- Graphics Hardware (2007) Timo Aila and Mark Segal (Editors)
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- 0-7803-8985-9/05/$20.00 2005 IEEE 21st IEEE SEMI-THERM Symposium Potential Thermal Security Risks
- Kevin Skadron University of Virginia
- 2007,KevinSkadron Implications of the Power Wall
- Reducing the Cost of Redundant Execution in Safety-Critical Systems using Relaxed Dedication
- On-Demand Solution to Minimize I-Cache Leakage Energy with Maintaining Performance
- IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS, VOL. 15, NO. 2, FEBRUARY 2007 159 Interconnect Lifetime Prediction for
- Intel Atom Processor Michelle McDaniel and Jonathan Dorn
- Freescale i. MX Feb 15, 2011
- Tilera (RAW) Processor Jason Mars and Robbie Hott
- CS 654 Fall 2002 Pipeline Simulator Exercise #2
- CS 6 5 4 F a ll 2 0 0 2 2 0 0 1 ,2 0 0 2 K e v in S k a d ro n
- Cell Broadband Architecture
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- 2002. Appears in the 2002 Workshop on Memory Performance Issues, in conjunction with ISCA-29; Anchorage, Alaska, May 25,2002. 1 Adaptive Cache Decay using Formal Feedback Control
- Control-Theoretic Techniques and Thermal-RC Modeling for Accurate and Localized Dynamic Thermal Management
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- Graphics Hardware (2004) T. Akenine-Mller, M. McCool (Editors)
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- 2GG(YHQ %XV ,QYHUW ZLWK 7ZR3KDVH 7UDQVIHU IRU %XVHV ZLWK &RXSOLQJ
- A Taxonomy of Branch Mispredictions, and Alloyed Prediction as a Robust Solution to Wrong-History Mispredictions
- LOW-POWER DESIGN AND TEMPERATURE MANAGEMENT
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- Power-Aware Branch Prediction: Characterization and Design
- dMT: inexpensive throughput enhancement in small-scale embedded microprocessors with
- HotSpot: a Dynamic Compact Thermal Model at the Processor-Architecture Level
- Parallelization of Particle Filter Algorithms Matthew A. Goodrum,*
- Enhancing Energy Efficiency in Multi-tier Web Server Clusters via Prioritization Tibor Horvath and Kevin Skadron
- Impact of Parameter Variations on Multi-Core Chips Eric Humenay, David Tarjan, Kevin Skadron
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- Using Performance Counters for Runtime Temperature
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- Potential Thermal Security Risks Puyan Dadvar
- Detection and Tracking of Human Subjects presented to
- MICRO-ARCHITECTURAL TEMPERATURE MODELING USING PERFORMANCE COUNTERS
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- A Measurement Platform for DVS Algorithm Development and Analysis
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- I N -S T AT / M D R F E B R U A R Y 2 , 2 0 0 4 M I C R O P R O C E S S O R R E P O R T simply isn't good enough to take a place at the top of Intel's
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- 610272-1732/00/$10.00 2000 IEEE The Itanium processor is the first
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- Testing the Feasibility of Running a Computationally Intensive Real-Time Traffic Simulation on a Multicore
- Design Space Exploration for Integrated CPU-GPU Chips University of Virginia, Charlottesville, VA 22904
- Temperature-Aware GPU Design Jeremy W. Sheaffer, Kevin Skadron, and David P. Luebke
- TemperatureAware Microarchitecture y Kevin Skadron, z Mircea R. Stan, z Wei Huang, y Sivakumar Velusamy,
- HotLeakage: A TemperatureAware Model of Subthreshold and Gate Leakage for Architects
- ControlTheoretic Techniques and ThermalRC Modeling for Accurate and Localized Dynamic Thermal Management
- Genetically Programmed Response Surfaces for Efficient Design Space Exploration
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- Leveraging Memory Level Parallelism Using Dynamic Warp Subdivision Jiayuan Meng, David Tarjan, Kevin Skadron
- Merging Path and Gshare Indexing in Perceptron Branch Prediction
- TSpec: A Notation for Describing Memory Reference Traces University of Virginia Department of Computer Science
- EXPERIENCES USING FPGAS FOR TEMPERATURE-AWARE MICROARCHITECTURE RESEARCH Siva Velusamy
- Federation: Repurposing Scalar Cores for Out-of-Order Instruction Issue
- An Improved Block-Based Thermal Model in HotSpot 4.0 with Granularity Considerations
- Abhishek RawatAbhishek Rawat Avinash KalyanaramanAvinash Kalyanaraman
- Power Issues Related to Branch Prediction --University Of Virginia Tech.Report CS-2001-25 --
- Accelerating SQL Database Operations on a GPU with CUDA
- Temperature-Aware Microarchitecture: Extended Discussion and Results UNIV. OF VIRGINIA DEPT. OF COMPUTER SCIENCE TECH. REPORT CS-2003-08
- Diana Lleva Julissa Campos
- Analysis of Thermal Monitor features of the Intel Pentium -M Processor Analysis of Thermal Monitor features of
- Control-Theoretic Dynamic Frequency and Voltage Scaling for Multimedia Workloads
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- CS 654 Fall 2001 Pipeline Simulator Exercise #1
- Applications of Small-Scale Reconfigurability to Graphics Processors
- Feasibility of Dynamic Binary Parallelization Jing Yang, Kevin Skadron, Mary Lou Soffa, and Kamin Whitehouse
- HotSpot--A Chip and Package Compact Thermal Modeling Methodology for VLSI Design
- The ARM11 Architecture Payton Oliveri
- Dynamic Warp Subdivision for Non-Speculative Runahead SIMT Gather Jiayuan Meng, Kevin Skadron
- Performance, Energy, and Thermal Considerations for SMT and CMP Architectures
- A Taxonomy of Branch Mispredictions, and Alloyed Prediction as a Robust Solution to WrongHistory Mispredictions
- STT-RAM for Shared Memory in GPUs Presented to
- 8th THERMINIC Workshop 14 October 2002, Madrid
- IEEE TRANSACTIONS ON COMPONENTS AND PACKAGING TECHNOLOGIES, VOL. 28, NO. 4, DECEMBER 2005 615 Parameterized Physical Compact Thermal Modeling
- Differential Multithreading: Recapturing Pipeline Stall Cycles and Enhancing Throughput in SmallScale Embedded Microprocessors
- Studying Thermal Management for Graphics-Processor Architectures Jeremy W. Sheaffer, Kevin Skadron, David P. Luebke
- The Effects of Context Switching on Branch Predictor Performance Michele Co and Kevin Skadron
- Memory Reference Reuse Latency: Accelerated Warmup for Sampled Microarchitecture
- Rodinia: A Benchmark Suite for Heterogeneous Computing Shuai Che, Michael Boyer, Jiayuan Meng, David Tarjan, Jeremy W. Sheaffer, Sang-Ha Lee and Kevin Skadron
- M. Guo et al. (Eds.): ISPA 2006, LNCS 4330, pp. 6374, 2006. Springer-Verlag Berlin Heidelberg 2006
- UNDERGRADUATE THESIS PROJECT FINAL REPORT School of Engineering and Applied Science
- Enabling Task Parallelism in the CUDA Scheduler Marisabel Guevara Chris Gregg Kim Hazelwood Kevin Skadron
- ADAPTIVE SECURITY POLICIES ENFORCED BY SOFTWARE DYNAMIC TRANSLATION
- In recent years, power density in microprocessors has doubled every three years,
- Hyper-Threading Technology Architecture and Microarchitecture 1 Hyper-Threading Technology Architecture and
- Experience Porting MATLAB Systems Biology Applications to CUDA LAVA: Laboratory for Computer Architecture at Virginia
- Inexpensive Throughput Enhancement in SmallScale Embedded Microprocessors with Block Multithreading: Extensions,
- Accurate Pre-RTL Temperature-Aware Design Using a Parameterized, Geometric
- GPUCT: A GPU-Accelerated CT Reconstruction System Presented to
- Power Consumption Characterization of a Graphics Processing Unit
- M I C R O D E S I G N R E S O U R C E S M A R C H 3 1 , 1 9 9 7 M I C R O P R O C E S S O R R E P O R T V O L . 1 1 , N O . 4
- Rodinia: A Benchmark Suite for Heterogeneous Computing LAVA: Laboratory for Computer Architecture at Virginia
- M I C R O D E S I G N R E S O U R C E S J A N U A R Y 2 6 , 1 9 9 8 M I C R O P R O C E S S O R R E P O R T by Peter Song
- PathBased Target Prediction for File System Prefetching Brian S. White Kevin Skadron
- BLP: Applying ILP Techniques to Bytecode Execution Kevin Scott and Kevin Skadron
- The Use of MiniVector Instructions for Implementing HighSpeed Feedback Controllers on GeneralPurpose
- Caches as Filters: A Unifying Model for Memory Hierarchy Analysis
- Experiences Accelerating MATLAB Systems Biology Applications
- Using Branch Prediction Information for Near-Optimal I-Cache Leakage Reduction University of Virginia, Department of Computer Science Tech Report CS-2006-03
- Impact of Process Variations on Multicore Performance Symmetry Eric Humenay, David Tarjan, Kevin Skadron
- Implementing Decay Techniques using 4T Quasi-Static Memory Cells
- ClassificationBased Hybrid Branch Prediction Presented to
- Supporting Higher-Order Controllers for Magnetic Bearings in a High-Speed, Real-Time Platform Using
- Physical Challenges in Reliable Graphics Hardware Design A Dissertation
- Automated Dynamic Analysis of CUDA Programs Michael Boyer
- IMPLEMENTING A DEFORMABLE MODEL IMAGE SEGMENTATION ALGORITHM FOR A MULTI-CORE
- The advance of technology scaling (along with resulting increases in power den-
- Analytical Model for Sensor Placement on Microprocessors Kyeong-Jae Lee, Kevin Skadron, and Wei Huang
- Characterizing Thermal Behavior of Pentium-IV with Hyperthreading
- Programming with Relaxed Streams Univ. of Virginia Dept. of Comp. Sci. Tech Report CS-2007-17
- Performance Modeling and Automatic Ghost Zone Optimization for Iterative Stencil Loops on GPUs
- 0018-9162/03/$17.00 2003 IEEE December 2003 35 G U E S T E D I T O R S ' I N T R O D U C T I O N
- ENERGY MANAGEMENT REAL-TIME MULTI-TIER INTERNET SERVICES
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- A Survey on ARM Cortex A Overview of ARM Processors
- fl2002. Appears in the 2002 Workshop on Memory Performance Issues, in conjunction with ISCA29; Anchorage, Alaska, May 25,2002. 1 Adaptive Cache Decay using Formal Feedback Control
- ArchitectureLevel Compact Thermal RC Modeling Marco Barcella, Wei Huang, Kevin Skadron, Mircea Stan
- TemperatureAware Microarchitecture: Extended Discussion and Results UNIV. OF VIRGINIA DEPT. OF COMPUTER SCIENCE TECH. REPORT CS200308 \Lambda
- NEC's Itanium prototype server (see Figure 1), code-named AzusA after a river
- Banking Chip Lifetime: Opportunities and Implementation Zhijian Lu, John Lach, Mircea Stan, Kevin Skadron
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- Power Issues Related to Branch Prediction Dharmesh Parikh y , Kevin Skadron y , Yan Zhang z , Marco Barcella z , Mircea R. Stan z
- Evaluating Reconfigurable Texture Units for Programmable Graphics Cards
- Minimal Subset Evaluation: Rapid Warm-up for Simulated Hardware State John W. Haskins, Jr. Kevin Skadron
- Subscribe Today | Contact Us | Re Home | Customer Service | Forums | Article Search | Product Reviews | Shop C
- Accelerating Leukocyte Tracking using CUDA: A Case Study in Leveraging Manycore Coprocessors
- Thermal Modeling and Management of Microprocessors A Dissertation
- CS 654 Fall 2003 Pipeline Simulator Exercise #1
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- Physically-Based Compact Thermal Modeling --Achieving Parametrization and Boundary Condition Independence
- Control-Theoretic Techniques and Thermal-RC Modeling for Accurate and Localized Dynamic Thermal Management
- 8th THERMINIC Workshop 1-4 October 2002, Madrid
- Subscribe Today | Contact Us | Re Home | Customer Service | Forums | Article Search | Product Reviews | Shop C
- Exploiting Inter-thread Temporal Locality for Chip Multithreading Jiayuan Meng
- Merging Path, Global and Local Indexing in Perceptron Branch Prediction
- Dynamic Way Allocation for High Performance, Low Power Caches Matthew Ziegler, Adam Spanberger, Ganesh Pai, Mircea Stan, Kevin Skadron
- Hybrid Architectural Dynamic Thermal Management Kevin Skadron
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- ControlTheoretic Techniques and ThermalRC Modeling for Accurate and Localized Dynamic Thermal Management
- ControlTheoretic Dynamic Frequency and Voltage Scaling for Multimedia Workloads
- Comparison of StatePreserving vs. NonStatePreserving Leakage Control in Caches \Lambda
- Abstract--We present a method for using programmable graphics hardware to solve a variety of boundary value problems.
- Accelerated Warmup for Sampled Microarchitecture Simulation
- An ahead pipelined alloyed perceptron with single cycle access time
- M I C R O D E S I G N R E S O U R C E S M A R C H 8 , 1 9 9 9 M I C R O P R O C E S S O R R E P O R T by Linley Gwennap
- Liang Wang Runjie Zhang IntroductionIntroduction
- M I C R O D E S I G N R E S O U R C E S N O V E M B E R 2 7 , 2 0 0 0 M I C R O P R O C E S S O R R E P O R T M I C R O P R O C E S S O R
- Techniques for Accurate, Accelerated Processor Simulation: An Analysis of Reduced Inputs and Sampling
- HydraScalar: A MultipathCapable Simulator \Lambda Kevin Skadron Pritpal S. Ahuja
- CS 654 Fall 2003 CS 654 Exercise #4
- Examining Suitability of Multicore Processor Architectures for Solving Realistic Computationally Intensive Problems by Simulating Synaptic Behavior in Large Neural
- State-Preserving vs. Non-State-Preserving Leakage Control in Caches , Dharmesh Parikh
- Hierarchical Domain Partitioning For Hierarchical Architectures Univ. of Virginia Dept. of Comp. Sci. Tech Report CS-2008-08
- Physically Constrained Architecture for Chip Multiprocessors A Dissertation
- Developing Visualization Tools for an Out-of-Order Execution Simulator
- CS 654 Fall 2003 SimpleScalar Familiarization Exercise
- VOLUME 13, NUMBER 7 MAY 31, 1999
- CS 654 Fall 2001 Out-of-Order Execution
- Dynamic Warp Subdivision for Integrated Branch and Memory Divergence Tolerance
- IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS, VOL. 14, NO. 5, MAY 2006 501 HotSpot: A Compact Thermal Modeling Methodology
- Avoiding Cache Thrashing due to Private Data Placement in Last-level Cache For Manycore Scaling
- Microarchitectural Floorplanning for Thermal Management: A Technical Report
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- Power-Aware Branch Prediction: Characterization and Design
- Compact Thermal Modeling for Temperature-Aware Design , Mircea R. Stan
- Procrastinating Voltage Scheduling with Discrete Frequency Sets Zhijian Lu, Yan Zhang, Mircea Stan, John Lach, Kevin Skadron
- Accelerating SQL Database Operations on a GPU with CUDA: Extended Results
- Dymaxion: Optimizing Memory Access Patterns for Heterogeneous Systems
- Scaling with Design Constraints Predicting the Future of Big Chips , Karthick Rajamani
- Automatic Intra-Application Load Balancing for Heterogeneous Systems
- Temperature-Aware Architecture: Lessons and Opportunities
- Dynamic Heterogeneous Scheduling Decisions Using Historical Runtime Data
- The increasing computational needs of parallel applications inevitably require portability across popular parallel architectures,
- Accelerating Braided B+ Tree Searches on a GPU with Jordan Fix, Andrew Wilkes, Kevin Skadron
- Cost-effective Safety and Fault Localization using Distributed Temporal Redundancy
- Reducing Power and Area by Interconnecting Memory Controllers to Memory Ranks with RF
- Bridging the Gap Between Theory and Hardware Mario Marino, Gabriel Robins, Kevin Skadron, and Liang Wang
- CS 6501 FPGA Familiarization Assignment The goal of this assignment is to give you an overview of the steps involved in programming an FPGA. As
- Accelerating Leukocyte Tracking Using CUDA
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- Robust SIMD: Dynamically Adapted SIMD Width and Multi-Threading Depth
- A Hierarchical Thread Scheduler and Register File for Energy-efficient Throughput Processors
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