Hauck, Scott - Department of Electrical Engineering, University of Washington at Seattle

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Hauck, Scott - Department of Electrical Engineering, University of Washington at Seattle

Design of a Real Time FPGAbased Three Dimensional Positioning Algorithm
Curriculum Vitae Ph.D., Computer Science & Engineering, University of Washington, 1995.
IEEE Symposium on FPGAs for Custom Computing Machines, 1998. Configuration Compression for the Xilinx XC6200 FPGA
IEEE Symposium on FPGAs for Custom Computing Machines, 1997. The Chimaera Reconfigurable Functional Unit
To appear in IEEE Transactions on VLSI Systems. High-Performance Carry Chains for FPGAs
MATCH: A MATLAB Compiler For Con gurable Computing P. Banerjee, N. Shenoy, A. Choudhary, S. Hauck, C. Bachmann
Active Learning Techniques in a CAD Course Scott Hauck
Predictive Coding of Hyperspectral Agnieszka C. Miguel
Append i x A . DNA De s i gn De t a i l s A DNA comparator accepts two strands of DNA as input and outputs the genetic distance
Automatic Layout of Domain-Specific Reconfigurable Subsystems for System-on-a-Chip
Exploration of RaPiD-style Pipelined FPGA Interconnects
Simultaneous Retiming and Placement for Pipelined Netlists Ken Eguro and Scott Hauck
Chapter 3. MultiFPGA System Applications In Chapter 2 we discussed many different implementation technologies for digital logic, considering
Chap t e r 5. Re s u l t s 5.1. Area Results
Accepted for publication in IEEE Transactions on VLSI Systems Configuration Relocation and Defragmentation for
STATIC VERSUS SCHEDULED INTERCONNECT IN COARSE-GRAINED RECONFIGURABLE ARRAYS
Submitted to IEEE Transactions on VLSI Systems. RUNLENGTH COMPRESSION TECHNIQUES FOR FPGA CONFIGURATIONS
Chapter 11. Logic Partition Orderings Introduction
Chapter 9. MultiFPGA System Software In Chapter 5 we presented numerous multiFPGA systems, and described the varied roles of these systems.
Application-Specific FPGA Synthesis Kenneth Eguro
IEEE Symposium on FPGAs for Custom Computing Machines, 1999. Abstract: Runlength Compression Techniques for FPGA Configurations1
Least-Significant Bit Optimization Techniques for Mark L. Chang and Scott Hauck
ACM/SIGDA Symposium on Field-Programmable Gate Arrays, pp. 29-36, 2001. Runtime and Quality Tradeoffs in
Precis: A User-Centric Wordlength Optimization Tool
Multi-Kernel Macah Support and Applications Adam Knight
A Comparison of Floating Point and Logarithmic Number Systems Michael Haselman, Michael Beauchamp,
Table of Contents LIST OF FIGURES ..................................................................................................................................... VI
Developing an Encryption-Specific FPGA Architecture Kenneth Eguro
Replication for Logic Partitioning A Project Report
ACM/SIGDA 2nd International Workshop on Field-Programmable Gate Arrays, Berkeley, February, 1994. Springbok: A Rapid-Prototyping System for Board-
TCAD 2181 1 Abstract--We present a pipelining-aware router for FPGAs.
Architecture-Adaptive Range Limit Windowing for Simulated Annealing FPGA Placement
Nathan G. Johnson-Williams, Student Member IEEE, Robert S. Miyaoka, Member IEEE, Xiaoli Li, Student Member IEEE, Tom K. Lewellen, Fellow IEEE, and Scott Hauck, Senior Member IEEE
PipeRoute: A Pipelining-Aware Router for FPGAs Akshay Sharma Carl Ebeling Scott Hauck
Architecture Development of Reconfigurable Encryption Hardware Kenneth Eguro and Scott Hauck
Chapter 7. Mesh Routing Topologies Introduction
Automatic Design of Reconfigurable Domain-Specific Flexible Cores
TCAD Revision of 3042 1 Enhancing Routing Heuristics on Pipelined-FPGAs
High Performance Carry Chains for FPGAs Matthew M. Hosler
Chap t e r 6. Conc l u s i on s In this study we wanted to generate a comparison of different fabrication technologies. A
Chapter 1. General Introduction In the mid 1980s a new technology for implementing digital logic was introduced, the fieldprogrammable
A Comparison of Floating Point and Logarithmic Number Systems for FPGAs
Issues of Wirelength Cost Models in Routing-Constrained FPGAs Kenneth Eguro and Scott Hauck
Chapter 2. Circuit Implementation Alternatives and Technologies Overview of chip design styles
Improved Configuration Prefetch for Single Context Reconfigurable Coprocessors
Design of a Second Generation Firewire Based Data Acquisition System for Small Animal PET Scanners T.K. Lewellen, Fellow IEEE, R.S. Miyaoka, Member IEEE, L.R. MacDonald, Member IEEE, M. Haselman, D. DeWitt,
Harnessing FPGAs for Computer Architecture Education Mark Holland, James Harris, Scott Hauck
IEEE Symposium on FPGAs for Custom Computing Machines, 2001. Totem: Custom Reconfigurable
The Future of Integrated Circuits: A Survey of Nano-electronics
Configuration Prefetching Techniques for Partial Reconfigurable Coprocessors with Relocation and
A Lemple -Ziv based Configuration Management Architecture
Abstract--This paper presents tools that automate the creation of domain-specific CPLDs, targeted for SoC. By
Chap t e r 1. I n t r oduc t i on Once a design for an integrated circuit has been conceived, a designer has four general options
Chap t e r 2. Techno l og i e s 2.1. Full Custom
Chapter 6. Springbok Introduction
Track Placement: Orchestrating Routing Structures
Chapter 8. Logic Emulator Interfaces Introduction
University Week Awards Issue 2010 Page By Hannah Hickey
The Totem Project by Katherine Compton and Scott Hauck
Abstract--When designing systems-on-a-chip (SoCs), a unique opportunity exists to generate custom FPGA architectures that are specific to
High-Performance Carry Chains for FPGAs Scott Hauck, Matthew M. Hosler, Thomas W. Fry
Architecture-Adaptive Routability-Driven Placement for FPGAs
International Conference on Computer-Aided Design, 1997. Replication for Logic Bipartitioning
Architecture Adaptive Routability-Driven Placement for FPGAs Akshay Sharma Carl Ebeling Scott Hauck
AUTOMATIC CREATION OF DOMAIN-SPECIFIC RECONFIGURABLE CPLDS FOR SOC Mark Holland, Scott Hauck
Harnessing FPGAs for Computer Architecture Education Mark Holland, James Harris, Scott Hauck
Proceedings of the IEEE, Vol. 86, No. 4, pp. 615-639, April, 1998. The Roles of FPGAs in Reprogrammable Systems
Harnessing FPGAs for Computer Architecture Education Mark Holland
Re f e r ence s [1] N. Ahmed, T. Natarajan, and K. R. Rao, "Discrete Cosine Transform," IEEE Transactions on
Hyperspectral Image Compression on Reconfigurable Platforms1 Thomas W. Fry
Automatic Layout of Domain Specific Reconfigurable Subsystems for System-on-a-Chip (SOC)
Accelerating Photoshop Applications with Reconfigurable Hardware Department of Electrical and Computer Engineering
Benchmarking the Independence Architecture Adaptive Placer on the Triptych FPGA Architecture
A Model for Programming Large-Scale Configurable Computing Applications
University of Washington, Dept. of CS&E TR #95-04-04, 1995. Achieving High-Latency, Low-Bandwidth
Managing short-lived and long-lived values in Coarse-Grained Reconfigurable Arrays
IEEE Transactions on VLSI Systems, Vol. 3, No. 4, pp. 473-482, December, 1995 Placement and Routing Tools for the Triptych FPGA
Chap t e r 4. Me t hodo l ogy One way to compare the relative performance of different technologies is to design and
TCAD 1687 1 Abstract--The development of domain-specialized
Automatic Design of Area-Efficient Configurable ASIC Cores
Impulse C vs. VHDL for Accelerating Tomographic Reconstruction , Nikhil Subramanian1
SPIHT Image Compression on FPGAs Thomas W. Fry
Submitted to IEEE Transactions on Design Automation of Electronic Systems. A previous version appeared in DAC'98 Data Security for Web-based CAD
Designing a Coarse-grained Reconfigurable Architecture for Power Efficiency Allan Carroll, Stephen Friedman, Brian Van Essen, Aaron Wood, Benjamin Ylvisaker,
Architecture-Adaptive Routability-Driven Placement Akshay Sharma1
University of Washington, Dept. of CSE, Technical Report, 1995. Multi-chip, board-level designs form a large portion of
Chapter 13. Conclusions and Future Work MultiFPGA systems is a growing area of research. They offer the potential to deliver high performance
Chapter 10. Bipartitioning Introduction
A C Compiler for a Processor with a Reconfigurable Functional Unit Alex Ye, Nagaraj Shenoy, Scott Hauck, Prithviraj Banerjee
Adaptive Computing in NASA Multi-Spectral Image Processing
Energy-Efficient Specialization of Functional Units in a Coarse-Grained Reconfigurable Array
ACM/SIGDA Workshop on Field-Programmable Gate Arrays, Berkeley, February, 1992. Routing-directed Placement for the TRIPTYCH FPGA
List of References [Actel94] FPGA Data Book and Design Guide, Sunnyvale, CA: Actel Corp, 1994.
DRAFT--Do not distribute Macah: A "C-Level" Language for Programming Kernels on
ARCHITECTURAL MODIFICATIONS TO IMPROVE FLOATING-POINT UNIT EFFICIENCY IN FPGAS
IEEE Transactions on VLSI Systems, Vol. 6, No. 3, pp. 400-408, Sept. 1998. 1999 IEEE Circuits and Systems Society TVLSI Best Paper. Mesh Routing Topologies for Multi-FPGA Systems
Digital Pulse Timing in FPGAs for Positron Emission Tomography. M.D. Haselman1
Configuration Compression for Virtex FPGAs Motorola Labs,
Chapter 5. MultiFPGA System Hardware In Chapter 3 we discussed the applications of multiFPGA systems, and concentrated on logic emulation in
Protecting regions of interest in medical images in a lossy packet network
SPR: An Architecture-Adaptive CGRA Mapping Tool Stephen Friedman
IEEE Design & Test of Computers, Vol. 11, No. 3, pp. 60-69, Fall, 1994. AN FPGA FOR IMPLEMENTING ASYNCHRONOUS CIRCUITS
Proceedings of the IEEE, Vol. 83, No. 1, pp. 69-93, January, 1995. Asynchronous Design Methodologies: An Overview
IEEE Trans. on CAD, Vol. 16, No. 8, pp. 849-866, August 1997. An Evaluation of Bipartitioning Techniques
IEEE Transactions on Computer-Aided Design of Integrated Circuits & Systems, Vol. 16, No. 9, pp. 956-964, September, 1997. Pin Assignment for Multi-FPGA Systems
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, Vol. 18, No. 8, pp. 1107-1113, August, 1999. Configuration Compression for the Xilinx XC6200 FPGA
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, Vol. 18, No. 9, pp. 1237-1248, September, 1999. Evaluation and Optimization of Replication Algorithms for Logic
206 IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS, VOL. 12, NO. 2, FEBRUARY 2004 The Chimaera Reconfigurable Functional Unit
Nathan G. Johnson-Williams, Student Member IEEE, Robert S. Miyaoka, Senior Member IEEE, Xiaoli Li, Student Member IEEE, Tom K. Lewellen, Fellow IEEE, and Scott Hauck, Senior Member IEEE
Runtime and Quality Tradeoffs in FPGA Placement and Routing
Development of a Place and Route Tool for the RaPiD Architecture
NORTHWESTERN UNIVERSITY Configuration Management Techniques for Reconfigurable
Unequal Loss Protection of Hyperspectral Compressed Images on Reconfigurable A project report submitted in partial fulfillment of the
A Comparison of Floating Point and Logarithmic Number Systems on FPGAs
An FPGA Implementation of Statistical Based Positioning
Building BLAST for Coprocessor Accelerators Using Macah
A FPGA Hardware Solution for Accelerating Tomographic Reconstruction
"C-Level" Programming of Parallel Coprocessor Accelerators Benjamin Ylvisaker
Improving the Energy Efficiency of Coarse-Grained Reconfigurable Arrays
An FPGA Acceleration of Short Read Human Genome Mapping Corey Bruce Olson
Advanced Research in VLSI and Parallel Systems: Proceedings of the 1992 Brown/MIT Conference, pp. 26-43, March, 1992.
International Conference on Computer Design, pp. 170-177, 1994. Mesh Routing Topologies For Multi-FPGA Systems
Chapel Hill Conference on Advanced Research in VLSI, pp. 383-402, March, 1995. An Evaluation of Bipartitioning Techniques
ACM/SIGDA International Symposium on Field-Programmable Gate Arrays, 1998. Configuration Prefetch for Single Context
Design Automation Conference, 1998. Data Security for Web-based CAD
ACM/SIGDA Symposium on Field-Programmable Gate Arrays, 1999. Don't Care Discovery for FPGA Configuration
A MATLAB Compiler For Distributed, Heterogeneous, Reconfigurable Computing Systems
IEEE Symposium on FPGAs for Custom Computing Machines, 2001. Configuration Compression for Virtex FPGAs
Configuration Prefetching Techniques for Partial Reconfigurable Coprocessor with Relocation and
Prcis: A Design-Time Precision Analysis Tool1 Mark L. Chang and Scott Hauck
PipeRoute: A Pipelining-Aware Router for FPGAs Akshay Sharma
Issues and Approaches to Coarse-Grain Reconfigurable Architecture Development Ken Eguro and Scott Hauck
Abstract--We present an algorithm for lossy compression of hyperspectral images generated by the MODIS instrument. To
Variable Precision Analysis for FPGA Synthesis Mark L. Chang and Scott Hauck
Reduced Complexity Wavelet-Based Predictive Coding of Hyperspectral Images for FPGA Implementation
Automated Least-Significant Bit Datapath Optimization for FPGAs
Automatic Creation of Reconfigurable PALs/PLAs for Mark Holland, Scott Hauck
Automating the Layout of Reconfigurable Subsystems Via Template Reduction
Accelerating FPGA Routing Using Architecture-Adaptive A* Techniques Akshay Sharma
Armada: Timing-Driven Pipeline-Aware Routing for FPGAs Ken Eguro and Scott Hauck
Embedded Floating-Point Units in FPGAs Michael J. Beauchamp Scott Hauck Keith D. Underwood K. Scott Hemmert
Improving Performance and Robustness of Domain-Specific CPLDs
Enhancing Timing-Driven FPGA Placement for Pipelined Netlists
FPGA-Based Front-End Electronics for Positron Emission Tomography
FPGA-Based Pulse Parameter Discovery for Positron Emission Tomography.
Dynamic Communication in a Coarse Grained Reconfigurable Array Robin Panda, Scott Hauck
H. Grunbacher, R. W. Hartenstein, Eds., Field-Programmable Gate Arrays: Architectures and Tools for Rapid Prototyping, Berlin: Springer-Verlag, pp. 44-51, 1993.
ACM/SIGDA 2nd International Workshop on Field-Programmable Gate Arrays, Berkeley, February, 1994. Mesh Routing Topologies For FPGA Arrays
IEEE Workshop on FPGAs for Custom Computing Machines, pp. 11-13, April, 1994. Pin Assignment for Multi-FPGA Systems
Probabilistic Auto-Tuning for Architectures with Complex Constraints
Automating the Layout of Reconfigurable Subsystems Via Template Shawn Phillips, Akshay Sharma, Scott Hauck
Simulation of Algorithms for Pulse Timing in Michael D. Haselman, Member IEEE, Scott Hauck, Senior Member IEEE, Thomas K. Lewellen,
FPGA-Based Data Acquisition System for a Positron Emission Tomography (PET) Scanner
Abstract--We report on the implementation of an algorithm and hardware platform to allow real-time processing of the
FPGA-Based Pulse Pileup Correction M.D. Haselman1
Northwestern University, Dept. of ECE, Technical Report, 1996. Software Technologies for Reconfigurable Systems
NorthwesternUniversity,Dept.ofECETechnicalReport,1997. Mapping Methods for the Chimaera Reconfigurable Functional Unit
CHIMAERA: Integrating a Reconfigurable Unit into a High-Performance, Dynamically-Scheduled Superscalar Processor
Configuration Relocation and Defragmentation for Reconfigurable Computing
Arithmetic Compression on SPIHT Encoded Images Todd Owen, Scott Hauck
Don't Care Discovery for FPGA Configuration Compression Motorola Labs
Reduced Complexity Wavelet-Based Predictive Coding of Hyperspectral Images for FPGA Implementation
Totem: Domain-Specific Reconfigurable Logic Scott Hauck1
Domain-Specific Reconfigurable PAL/PLA Creation for SoC
Enhanced Loop Flattening for Software Pipelining of Arbitrary Loop Nests
Runlength Compression Techniques for FPGA Configurations Scott Hauck, William D. Wilson
Military and Aerospace Applications of Programmable Devices and Technologies, 1999. Adaptive Computing in NASA Multi-Spectral Image Processing
CHIMAERA: A High-Performance Architecture with a Tightly-Coupled Reconfigurable Functional Unit
A C-to-FPGA Solution for Accelerating Tomographic Reconstruction
Beauchamp -TVLSI-00112-2006 Architectural Modifications to Enhance the
FPGA vs. MPPA for Positron Emission Tomography Pulse Processing
Software Managed Distributed Memories in MPPAs Robin Panda, Jimmy Xu, Scott Hauck
APHYDS: The Academic Physical Design Skeleton Scott Hauck
Chapter 12. Pin Assignment Introduction
Chapter 4. Logic Validation Logic emulation is one of the most promising application domains for multiFPGA systems. In this chapter
Chap t e r 3. C i r cu i t s To assess the relative merits of each technology, circuits were designed and then implemented in
W. Moore, W. Luk, Eds., FPGAs, Oxford: Abingdon EE&CS Books, pp. 75-90, 1991. TRIPTYCH: A New FPGA Architecture
Harnessing FPGAs for Computer Architecture Education Mark Holland, James Harris, Scott Hauck
Evolution of the Design of a Second Generation FireWire Based Data Acquisition System
Accelerating Statistical LOR Estimation for a High-Resolution PET Scanner using FPGA Devices and a High Level Synthesis Tool
I. INTRODUCTION eveloping new detector designs for PET and SPECT
ACM/SIGDA International Symposium on Field-Programmable Gate Arrays, pp. 32-38, February, 1995. Logic Partition Orderings for Multi-FPGA Systems
IEEE Transactions on VLSI Systems, Vol. 3, No. 4, pp. 473-482, December, 1995 The Triptych FPGA Architecture
Medical Imaging Process Accelerated in FPGA Hardware by 82x over Software Line of Reaction Estimation for a PET scanner Optimized using C to FPGA Methodology
Dataflow-Driven Execution Control in a Coarse-Grained Reconfigurable Array
Multi-Kernel Floorplanning for Enhanced CGRAs Aaron Wood
Evolution of the Design of a Second Generation FireWire Based Data Acquisition System
Architecture and Compiler Support for a VLIW Execution Model on a Coarse-Grained Reconfigurable Array
UNIVERSITYOFWASHINGTON Hephaestus
Figure 1: Short read mapping aligns reads to a reference genome in the presences of errors and genetic variations.
FPGA-Based Pulse Pile-up Correction M.D. Haselman1