- A Statistical Fault Coverage Metric for Realistic Path Delay Faults Wangqi Qiu*
- At-Speed Test for Path Delay Faults Using Practical Techniques Wangqi Qiu*
- Process Variation Dimension Reduction Based on SVD Zhuo Li, Xiang Lu and Weiping Shi
- Impact of Photolithography and Mask Variability on Interconnect Parasitics *
- IEEE TRANSACTIONS ON COMPUTER-AIDED DESIGN OF INTEGRATED CIRCUITS AND SYSTEMS, VOL. 24, NO. 6, JUNE 2005 879 A Fast Algorithm for Optimal Buffer Insertion
- STRUCTURAL DIAGNOSIS OF WIRING NETWORKS: FINDING CONNECTED COMPONENTS OF UNKNOWN SUBGRAPHS
- IEEE TRANSACTIONS ON VLSI SYSTEMS, VOL. 3, NO. 3, SEPTEMBER 1995 1 Optimal Interconnect Diagnosis of Wiring Networks
- Minimum Moment Steiner Trees Weiping Shi
- A New Methodology for Interconnect Parasitics Extraction Considering Photo-Lithography Effects .
- DIAGNOSIS OF WIRING NETWORKS: AN OPTIMAL RANDOMIZED ALGORITHM FOR FINDING CONNECTED
- Making Fast Buffer Insertion Even Faster Via Approximation Techniques , C. N. Sze1
- An O(mn) Time Algorithm for Optimal Buffer Insertion of Nets with m Sinks
- IEEE TRANSACTIONS ON COMPUTER-AIDED DESIGN OF INTEGRATED CIRCUITS AND SYSTEMS VOL. XX, NO. Y, MONTH 200X 1 Time Algorithm for Optimal Buffer Insertion with
- SIAM J. COMPUT. c 2006 Society for Industrial and Applied Mathematics Vol. 35, No. 3, pp. 729740
- W. Shi, J. Liu, N. Kakani and T. Yu Department of Electrical Engineering
- Improving Boundary Element Methods for Parasitic Extraction Shu Yan Jianguo Liu Weiping Shi
- PARADE: PARAmetric Delay Evaluation Under Process Variation* (Revised Version)
- A Circuit Level Fault Model for Resistive Shorts of MOS Gate Oxide , Wangqi Qiu
- An Optimal Test Pattern Selection Method to Improve the Defect Coverage Yuxin Tian, Michael R. Grimaila, Weiping Shi and M. Ray Mercer
- Single Tree Grammars1 Sheila Greibach2, Weiping Shi3 and Shai Simonson4
- IEEE TRANSACTIONS ON COMPUTER-AIDED DESIGN OF INTEGRATED CIRCUITS AND SYSTEMS, VOL. 15, NO. 12, DECEMBER 19961 A Fast Algorithm for Area Minimization of Slicing
- Complexity Analysis and Speedup Techniques for Optimal Buffer Insertion with Minimum Cost
- Making Fast Buffer Insertion Even Faster via
- Fast Capacitance Extraction Using Inexact Factorization
- K Longest Paths Per Gate (KLPG) Test Generation for Scan-Based Sequential Circuits Wangqi Qiu, Jing Wang, D. M. H. Walker, Divya Reddy+
