- Abstract--A wide variety of DSP design tools have been developed that incorporate dataflow graph representations into
- Porting DSP Applications across Design Tools Using the Dataflow Interchange Format
- springer.com Springer Berlin Heidelberg New York
- Distributed embedded computing systems are special-purpose computer systems designed for particular applications and set up in a networked or distributed manner. A
- Parameterized Modeling and Scheduling for Dataflow Bishnupriya Bhattacharya and Shuvra S. Bhattacharyya
- Integrating VSIPL Support in the Dataflow Interchange Format Chia-Jui Hsu and Shuvra S. Bhattacharyya
- Title of Document: HIGH-PERFORMANCE 3D IMAGE PROCESSING ARCHITECTURES FOR
- Buffer Merging --A Powerful Technique for Reducing Memory Requirements of Synchronous Dataflow Specifications
- Journal of VLSI Signal Processing 43, 247258, 2006 c 2006 Springer Science + Business Media, LLC. Manufactured in The Netherlands.
- Efficient Simulation of Critical Synchronous Dataflow Graphs
- Quasi-static Scheduling of Reconfigurable Dataflow Graphs for DSP Systems Bishnupriya Bhattacharya and Shuvra S. Bhattacharyya,
- Title of Dissertation : PERFORMANCE ANALYSIS AND HIERARCHICAL TIMING FOR DSP SYSTEM
- Optimization Tradeoffs in the Synthesis of Software for Embedded DSP Shuvra S. Bhattacharyya
- RESYNCHRONIZATION FOR MULTIPROCESSOR DSP IMPLEMENTATION ---PART 1: MAXIMUM THROUGHPUTRESYNCHRONIZATION 1
- System Synthesis for Polymorphous Computing Architectures Sumit Lohani and Shuvra S. Bhattachrayya
- Computer vision has emerged as one of the most popular domains of embedded appli-cations. Though various new powerful embedded platforms to support such applica-
- An Integrated ASIP Design Flow for Digital Signal Processing Applications
- Optimized Software Synthesis for Digital Signal Processing Algorithms --
- Contentionconscious Transaction Ordering in Embedded Multiprocessors Systems 1
- SYSTEMATIC CONSOLIDATION OF INPUT AND OUTPUT BUFFERS IN SYNCHRONOUS DATAFLOW
- Affine Nested Loop Programs and their Binary Parameterized Dataflow Graph Counterparts
- A Communication Interface for Multiprocessor Signal Processing Systems Sankalita Saha
- Intermediate Representations for Design Automation of Multiprocessor DSP Systems
- Dataflow-based Implementation of Model Predictive Control Ruirui Gu, member IEEE, Shuvra S. Bhattacharyya, senior member IEEE and Williams S. Levine, IEEE fellow
- IEEE SIGNAL PROCESSING MAGAZINE [24] NOVEMBER 2009 [from the GUEST EDITORS]
- Renesting Single Appearance Schedules to Minimize Buffer Memory Shuvra S. Bhattacharyya, Praveen K. Murthy, and Edward A. Lee
- SPECIAL ISSUE Model-based mapping of reconfigurable image registration
- A Component Architecture for FPGA-based, DSP System Design Gary Spivey*
- In Proc. of the IEEE Workshop on Signal Processing Systems, Boston, October 1998, c IEEE Optimized Software Synthesis for Digital Signal
- Title of Dissertation: COMMUNICATION-DRIVEN CODESIGN FOR MULTIPROCESSOR SYSTEMS
- Energy-Efficient Multi-processor Implementation of Embedded Software
- Consistency Analysis of Reconfigurable Dataflow Specifications1
- J Sign Process Syst (2011) 63:251263 DOI 10.1007/s11265-009-0399-3
- A Low-overhead Scheduling Methodology for Fine-grained Acceleration of Signal
- SYSTEMATIC EXPLOITATION OF DATA PARALLELISM IN HARDWARE SYNTHESIS OF DSP APPLICATIONS1
- References 1 [1] S. S. Bhattacharyya, S. Sriram, and E. A. Lee, Optimizing
- SCALABLE REPRESENTATION OF DATAFLOW GRAPH STRUCTURES USING TOPOLOGICAL PATTERNS
- Exploring the Probabilistic Design Space of Multimedia Systems Shaoxiong Hua, Gang Qu, and Shuvra S. Bhattacharyya
- SYSTEM SYNTHESIS FOR OPTICALLY-CONNECTED, MULTIPROCESSORS ON-CHIP
- IEEE SIGNAL PROCESSING MAGAZINE [20] MARCH 2010 [from the GUEST EDITORS]
- IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS--II: ANALOG AND DIGITAL SIGNAL PROCESSING, VOL. 47, NO. 9, SEPTEMBER 2000 849 Software Synthesis and Code Generation for
- Applying Graphics Processor Acceleration in a Software Defined Radio Prototyping Environment
- Efficient Techniques for Clustering and Scheduling onto Embedded Multiprocessors
- Journal of VLSI Signal Processing Systems 24, 8398 (2000) c 2000 Kluwer Academic Publishers, Boston. Manufactured in The Netherlands.
- APGAN and RPMC: Complementary Heuristics for Translating DSP Block Diagrams into Efficient Software Implementations
- Parameterized Modeling and Scheduling of Dataflow Bishnupriya Bhattacharya and Shuvra S. Bhattacharyya
- The DSPCAD Integrative Command Line Environment: Introduction to DICE Version 1
- Cycle-Breaking Techniques for Scheduling Synchronous Dataflow Graphs
- System Synthesis for Polymorphous Computing Architectures Sumit Lohani and Shuvra S. Bhattachrayya
- Parallel Problem Solving from Nature --PPSN V, Amsterdam, The Netherlands, September 1998, pages 885--894. c flSpringer.
- 978-1-4244-4620-9/09/$25.00 c 2009 IEEE Resource-efficient Acceleration of 2-Dimensional
- Negative Cycle Detection in Dynamic Graphs UMIACSTR9959/CSTR4065
- Efficient Simulation of Critical Synchronous Dataflow Graphs
- OpenDF A Dataflow Toolset for Reconfigurable Hardware and Multicore Systems
- A Period Graph Throughput Estimator for Multiprocessor Systems1
- OPTIMAL PARENTHESIZATION OF LEXICAL ORDERINGS FOR DSP BLOCK DIAGRAMS1
- A Rapid Prototyping Methodology for Application-Specific Sensor Networks Chung-Ching Shen, Celine Badr, Kamiar Kordari, Shuvra S. Bhattacharyya,
- Multiobjective Optimization of FPGA-Based Medical Image Registration Omkar Dandekar1,2
- EXPLOITING STATICALLY SCHEDULABLE REGIONS IN DATAFLOW PROGRAMS Ruirui Gu, Jorn W. Janneck, Mickael Raulet, Shuvra S. Bhattacharyya
- [21] M. Veiga, J. Parera, and J. Santos, ``Programming DSP Systems on Multiprocessor Architectures,'' Proceedings of the International Conference on Acoustics, Speech, and Signal Processing, Albuquerque, p. 9658 vol.2, April,
- SYSTEMATIC GENERATION OF FPGA-BASED FFT IMPLEMENTATIONS Hojin Kee1, Newton Petersen2, Jacob Kornerup2, Shuvra S. Bhattacharyya1
- Communication Strategies for Shared-Bus Embedded Multiprocessors
- Functional DIF for Rapid Prototyping William Plishker, Nimish Sane, Mary Kiemb, Kapil Anand, and Shuvra S. Bhattacharyya
- MODELING OF BLOCK-BASED DSP SYSTEMS Dong-Ik Ko and Shuvra S. Bhattacharyya
- Optimization of Signal Processing Software for Control System Implementation
- Register File Partitioning with Constraint Programming
- Design and Implementation of Real-time Signal Processing Applications on Heterogeneous Multiprocessor Arrays
- Approximation Algorithms and Heuristics for the Dynamic Storage Allocation Problem Praveen K. Murthy
- 682 IEEE SENSORS JOURNAL, VOL. 8, NO. 6, JUNE 2008 Sensor Support Systems for Asymmetric
- Latencyconstrained Resynchronization for Multiprocessor DSP Implementation
- DIF: An Interchange Format for Dataflow-based Design Tools
- A Model-based Schedule Representation for Heterogeneous Mapping of Dataflow Hsiang-Huang Wu, Chung-Ching Shen, Nimish Sane, William Plishker, Shuvra S. Bhattacharyya
- CHARMED: A Multi-objective Co-synthesis Framework for Multi-mode Embedded Systems
- Shared Memory Implementations of Synchronous Dataflow Specifications Using Lifetime Analysis Techniques
- Catalog no. 3096, March 2006, c. 1352 pp. in 2 volumes ISBN: 0-8493-3096-3, $149.95 / 85.00
- Abstract --Distributed sensor system applications (e.g., wire-less sensor networks) have been studied extensively in recent
- Improving the Performance of Active Set Based Model Predictive Controls by Dataflow Methods
- In this paper, we explore a hybrid global/local search optimization framework for dynamic voltage scaling in embedded multiproces-
- MODELING AND OPTIMIZATION OF BUFFERING TRADE-OFFS FOR HARDWARE IMPLEMENTATION OF IMAGE PROCESSING APPLICATIONS
- An Architectural Level Design Methodology for Embedded Face Detection
- AUTOMATED GENERATION OF AN EFFICIENT MPEG-4 RECONFIGURABLE VIDEO CODING DECODER IMPLEMENTATION
- Goal-Driven Reconfiguration of Polymorphous Architectures
- Logic Foundry: A Rapid Prototyping Tool for FPGA-based DSP Systems Gary Spivey
- Mode Grouping for More Effective Generalized Scheduling of Dynamic Dataflow Applications
- Software Synthesis and Code Generation for Signal Processing Systems \Lambda
- 978-1-4244-1694-3/08/$25.00 2008 IEEE In this paper, we present the design and implementa-
- Page 1 of 2 Page 1 of 2
- 3126 IEEE TRANSACTIONS ON SIGNAL PROCESSING, VOL. 55, NO. 6, JUNE 2007 Parameterized Looped Schedules for Compact
- [dsp FORUM] Shuvra S. Bhattacharyya, Jeff Bier,
- Journal of Signal Processing Systems 50, 163177, 2008 * 2007 Springer Science + Business Media, LLC. Manufactured in The United States.
- This paper is concerned with the compact representa-tion of execution sequences in terms of efficient looping
- Analysis of Dataflow Programs with Interval-limited Jurgen Teich
- RESYNCHRONIZATION FOR MULTIPROCESSOR DSP SYSTEMS ---PART 2: LATENCYCONSTRAINED RESYNCHRONIZATION 1
- Buffer Merging --A Powerful Technique for Reducing Memory Requirements of Synchronous Dataflow
- Heterogeneous Design in Functional DIF William Plishker, Nimish Sane, Mary Kiemb, and Shuvra S. Bhattacharyya
- J Sign Process Syst DOI 10.1007/s11265-009-0445-1
- Springer.com Handbook of Signal Processing Systems
- Dynamic and Multidimensional Data ow Shuvra S. Bhattacharyya, Ed F. Deprettere, and Joachim Keinert
- Methods for Efficient Implementation of Model Predictive Control on Multiprocessor Systems
- Title of thesis: DESIGN AND TESTING METHODOLOGIES FOR SIGNAL PROCESSING SYSTEMS
- Title of dissertation: SYSTEMATIC EXPLORATION OF TRADE-OFFS BETWEEN APPLICATION THROUGHPUT AND
- Efficient Static Buffering to Guarantee Throughput-Optimal FPGA Implementation of
- BUFFER MANAGEMENT FOR MULTI-APPLICATION IMAGE PROCESSING ON MULTI-CORE PLATFORMS: ANALYSIS AND CASE STUDY
- LOOP TRANSFORMATIONS FOR INTERFACE-BASED HIERARCHIES IN SDF GRAPHS Jonathan Piat1
- IEEE SIGNAL PROCESSING MAGAZINE [61] MARCH 20101053-5888/10/$26.002010IEEE Utilizing Hierarchical
- Model-based DSP Implementation on FPGAs William Plishker, Chung-Ching Shen, Shuvra S. Bhattacharyya
- Rapid Prototyping for Digital Signal Processing Systems using Parameterized Synchronous Dataflow Graphs
- Using the DSPCAD Integrative Command-Line Environment: User's Guide for DICE Version 1.0
- Guest Editorial: Special Issue on Multi-Core Enabled Multimedia Applications & Architectures
- 1646 IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS FOR VIDEO TECHNOLOGY, VOL. 19, NO. 11, NOVEMBER 2009 Exploring the Concurrency of an MPEG RVC
- High-performance buffer mapping to exploit DRAM concurrency in multiprocessor DSP systems
- IEEE TRANSACTIONS ON BIOMEDICAL CIRCUITS AND SYSTEMS, VOL. 3, NO. 6, DECEMBER 2009 361 Special Issue on Selected Papers
- A Generalized Scheduling Approach for Dynamic Dataflow Applications
- Sundararajan Sriram Shuvra S. Bhattacharyya
- Integration of Data ow Optimization Techniques into a Software Radio Design Framework
- A Generalized Static Data Flow Clustering Algorithm for MPSoC Scheduling of Multimedia Applications
- 1-4244-2542-6/08/$20.00 2008 IEEE Vladimir Guzma*, Shuvra S. Bhattacharyyat , Pertti Kellomaki*, and Jarmo Takala*
- Multithreaded Simulation for Synchronous Dataflow Graphs
- Towards Systematic Exploration of Tradeoffs for Medical Image Registration on Heterogeneous Platforms
- DESIGN METHODOLOGY FOR EMBEDDED COMPUTER VISION SYSTEMS
- A PARAMETERIZED DESIGN FRAMEWORK FOR HARDWARE IMPLEMENTATION OF PARTICLE FILTERS
- Energy Efficient Implementation of G.729 for Wireless VoIP Application
- Technical Report UMIACS-TR-2007-32, Institute for Advanced Computer Studies,
- Beyond Single-Appearance Schedules: Efficient DSP Software Synthesis Using
- Abstract--For the past decade, improving the performance and accuracy of medical image registration has been a driving
- EFFICIENT PARALLEL MEMORY ORGANIZATION FOR TURBO DECODERS Perttu Salmela, Ruirui Gu*, Shuvra S. Bhattacharyya*, and Jarmo Takala
- Hindawi Publishing Corporation EURASIP Journal on Embedded Systems
- ISDRS 2007, December 12-14, 2007, College Park, MD, USA ISDRS 2007 http://www.ece.umd.edu/ISDRS
- Compact, Low Power Wireless Sensor Network System for Line Crossing Recognition
- DIFdoc: a standard format for visualizing hierarchical dataflow representations
- MAPPING MULTIMEDIA APPLICATIONS ONTO CONFIGURABLE HARDWARE WITH PARAMETERIZED CYCLO-STATIC DATAFLOW GRAPHS
- Energy-Efficient Embedded Software Implementation on Multiprocessor
- 556 IEEE TRANSACTIONS ON SIGNAL PROCESSING, VOL. 54, NO. 2, FEBRUARY 2006 Contention-Conscious Transaction Ordering in
- Over the past few decades, embedded systems have been widely infiltrated into our daily lives. Prominent examples are cellular phones, personal digital assistants,
- Signal processing applications usually encounter multi-dimensional real-time per-formance requirements and restrictions on resources, which makes software implementa-
- Effective Strategies for Aggressive Memory Optimization
- Compression Techniques for Minimum Energy Consumption
- DYNAMIC CONFIGURATION OF DATAFLOW GRAPH TOPOLOGY FOR DSP SYSTEM DESIGN Dong-Ik Ko and Shuvra S. Bhattacharyya
- MODELING OF BLOCK-BASED DSP SYSTEMS Dong-Ik Ko and Shuvra S. Bhattacharyya
- MODELING IMAGE PROCESSING SYSTEMS WITH HOMOGENEOUS PARAMETERIZED DATAFLOW GRAPHS
- Computer Vision on FPGAs: Design Methodology and its Application to Gesture Recognition
- Interconnect Synthesis for Systems on Chip Neal K. Bambha and Shuvra S. Bhattacharyya
- IEEE TRANSACTIONS ON EVOLUTIONARY COMPUTATION, VOL. 8, NO. 2, APRIL 2004 137 Systematic Integration of Parameterized Local Search
- Journal of VLSI Signal Processing 38, 131146, 2004 c 2004 Kluwer Academic Publishers. Manufactured in The Netherlands.
- IEEE TRANSACTIONS ON SIGNAL PROCESSING, VOL. 52, NO. 5, MAY 2004 1209 The Hierarchical Timing Pair Model for Multirate
- Technical Report #UMIACS-TR-2004-66, Institute for Advanced Computer Studies, University of Maryland at College Park, November 2004
- Compact Procedural Implementation in DSP Software Synthesis through Recursive Graph
- Compact Procedural Implementation in DSP Software Synthesis through Recursive Graph
- The Java programming language is acheiving greater accep-tance in high-end embedded systems such as cellphones and
- Design Considerations for Optically Connected Systems on Chip Neal K. Bambha and Shuvra S. Bhattacharyya
- about the book. . . Rangingfrom low-level applicationandarchitectureoptimizationsto high-levelmodeling
- Data Partitioning for DSP Software Synthesis
- A Modular Genetic Algorithm for Scheduling Task Graphs
- Logic Foundry: Rapid Prototyping of FPGA-based DSP Systems Gary Spivey
- Hardware/Software Co-synthesis of DSP Systems Shuvra S. Bhattacharyya
- ADAPTIVE NEGATIVE CYCLE DETECTION IN DYNAMIC GRAPHS Nitin Chandrachoodan, Shuvra S. Bhattacharyya
- THE HIERARCHICAL TIMING PAIR MODEL Nitin Chandrachoodan, Shuvra S. Bhattacharyya
- Multiprocessor Clustering for Embedded System Implementation1 Vida Kianzad and Shuvra S. Bhattacharyya
- IEEE TRANSACTIONS ON COMPUTER-AIDED DESIGN OF INTEGRATED CIRCUITS AND SYSTEMS, VOL. 20, NO. 2, FEBRUARY 2001 177 Shared Buffer Implementations of Signal Processing
- A critical challenge in synthesis techniques for itera-tive applications is the efficient analysis of performance in
- Memory consumption is an important metric during software synthesis from block-diagram specifications of DSP applica-
- Real-Time Memory Management: Compile-Time Techniques and Run-Time Mechanisms that Enable the Use of Caches
- Contention-conscious Transaction Ordering in Embedded Multiprocessors1
- Shared Memory Implementations of Synchronous Dataflow Specifications Praveen K. Murthy
- 452 IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS, VOL. 8, NO. 4, AUGUST 2000 EXPERIMENTAL RESULTS
- Optimization Trade-offs in the Synthesis of Software for Embedded DSP Shuvra S. Bhattacharyya
- The CBP Parameter --a Useful Annotation to Aid SDF Compilers 1 of 20 The CBP Parameter --a Useful Annotation to
- A Buffer Merging Technique for Reducing Memory Requirements of Synchronous Dataflow Specifications
- Parallel Problem Solving from Nature { PPSN V, Amsterdam, The Netherlands, September 1998, pages 885{894. c Springer. Bu er memory optimization in DSP applications
- Since software prototypes of DSP applications are most efficient when their code and data space require-
- A HIERARCHICAL MULTIPROCESSOR SCHEDULING FRAMEWORK FOR SYNCHRONOUS DATAFLOW GRAPHS
- LOOPED SCHEDULES FOR DATAFLOW DESCRIPTIONS OF MULTIRATE SIGNAL PROCESSING ALGORITHMS1
- Title of dissertation: System Synthesis for Embedded Multiprocessors Vida Kianzad, Doctor of Philosophy, 2006
- Optimizing the Efficiency of Parameterized Local Search within Global Search: A Preliminary Study
- IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS--I: FUNDAMENTAL THEORY AND APPLICATIONS, VOL. 47, NO. 11, NOVEMBER 2000 1597 Resynchronization for Multiprocessor DSP Systems
- HETEROGENEOUS MODELING AND
- Abstract--Most image processing applications are character-ized by computation-intensive operations, and high memory and
- S. Vassiliadis et al. (Eds.): SAMOS 2006, LNCS 4017, pp. 142 154, 2006. Springer-Verlag Berlin Heidelberg 2006
- A Comparison of Clustering and Scheduling Techniques for Embedded Multiprocessor Systems
- Int. J. Embedded Systems, Vol. 4, No. 1, 2009 83 An architectural level design methodology for smart
- How to make stream processing more mainstream Shuvra S. Bhattacharyya
- Joint Application Mapping/Interconnect Synthesis Techniques for Embedded
- Multiprocessor Clustering for Embedded Systems1 Vida Kianzad and Shuvra S. Bhattacharyya
- Marcel Dekker Catalog: Embedded Multiprocessors Page 1 of 1 http://www.dekker.com/e/p.pl/9318-8?frame=main 3/4/00
- SIMULATING DYNAMIC COMMUNICATION SYSTEMS USING THE CORE FUNCTIONAL DATAFLOW MODEL
- An Optimized Message Passing Framework for Parallel Implementation of Signal Processing Applications
- ENERGY-AWARE DATA COMPRESSION FOR WIRELESS SENSOR NETWORKS Sebastian Puthenpurayil, Ruirui Gu, Shuvra S Bhattacharyya
- TITLE: MODELING AND OPTIMIZATION TECHNIQUES FOR EFFICIENT IMPLEMENTATION OF
- First Version of a Dataflow Interchange Format1 Fuat Keceli, Mingyung Ko, Shahrooz Shahparnia, and
- Dataflow Transformations in High-level DSP System Design
- Software Synthesis from the Dataflow Interchange Format Chia-Jui Hsu, Ming-Yung Ko, and Shuvra S. Bhattacharyya
- Buffer Merging ---A Powerful Technique for Reducing Memory Requirements of Synchronous Dataflow Specifications
- The CBP Parameter ---a Useful Annotation to Aid SDF Compilers 1 of 20 The CBP Parameter ---a Useful Annotation to
- Optimized Software Synthesis for DSP Using Randomization Techniques
- In Proc. of the IEEE Workshop on Signal Processing Systems, Boston, October 1998, c Optimized Software Synthesis for Digital Signal
- Journal of VLSI Signal Processing 21, 151166 (1999) c 1999 Kluwer Academic Publishers. Manufactured in The Netherlands.
- High-Level Synthesis of DSP Applications using Adaptive Negative Cycle Detection
- Energy-driven Distribution of Signal Processing Applications across Wireless Sensor Networks
- Title of dissertation: DATAFLOW INTEGRATION AND SIMULATION TECHNIQUES
- 2408 IEEE TRANSACTIONS ON SIGNAL PROCESSING, VOL. 49, NO. 10, OCTOBER 2001 Parameterized Dataflow Modeling for DSP Systems
- RECONFIGURABLE IMAGE REGISTRATION ON FPGA PLATFORMS Mainak Sen1
- Abstract--Digital signal processing (DSP) applications involve processing long streams of input data. It is important to take into
- LOW-OVERHEAD RUN-TIME SCHEDULING FOR FINE-GRAINED ACCELERATION OF SIGNAL PROCESSING SYSTEMS
- PARAMETERIZED DATAFLOW MODELING OF DSP SYSTEMS Bishnupriya Bhattacharya and Shuvra S. Bhattacharyya
- Evolutionary Algorithm Based Exploration of Software Schedules for Digital Signal Processors
- The Pipeline Decomposition Tree: An Analysis Tool For Multiprocessor Implementation Of
- MINIMIZING MEMORY REQUIREMENTS FOR CHAIN-STRUCTURED SYNCHRONOUS DATAFLOW
- Model-based design has been touted as the most viable design methodology of the future for the design of embedded hardware/software systems. Due to the large complex-
- FPGA-BASED DESIGN AND IMPLEMENTATION OF THE 3GPP-LTE PHYSICAL LAYER USING PARAMETERIZED SYNCHRONOUS DATAFLOW TECHNIQUES
- System-level Clustering and Timing Analysis for GALS-based Dataflow Architectures
- A DESIGN TOOL FOR EFFICIENT MAPPING OF MULTIMEDIA APPLICATIONS ONTO HETEROGENEOUS PLATFORMS
- COMPILING DATAFLOW PROGRAMS FOR DIGITAL SIGNAL PROCESSING
- Wireless sensor network (WSN) applications have been studied extensively in recent years. Such applica-
- The Signal Passing Interface and Its Application to Embedded
- A Lightweight Dataflow Approach for Design and Implementation of SDR Systems
- Using the DSPCAD Integrative Command-Line Environment: User's Guide for DICE Version 1.1
- The DSPCAD Integrative Command Line Environment: Introduction to DICE Version 1.1
- Dataflow-based Design and Implementation of Image Processing Applications
- MODEL-BASED PRECISION ANALYSIS AND OPTIMIZATION FOR DIGITAL SIGNAL PROCESSORS
- Modeling and Optimization of Dynamic Signal Processing in Resource-Aware Sensor Networks
- Title of thesis: REPRESENTATION AND SCHEDULING OF SCALABLE DATAFLOW GRAPH TOPOLOGIES
- Teaching Cross-Platform Design and Testing Methods for Embedded Systems using DICE
- Title of dissertation: RAPID PROTOTYPING OF HIGH PERFORMANCE
- Mapping Parameterized Cyclo-static Dataflow Graphs onto Configurable Hardware
- The DSPCAD Lightweight Dataflow Environment: Introduction to LIDE Version 0.1
- Topological patterns for scalable representation and analysis of dataflow graphs
- Heterogeneous Design in Functional DIF William Plishker, Nimish Sane, Mary Kiemb, and Shuvra S. Bhattacharyya
- Multithreaded Simulation for Synchronous Dataflow Graphs CHIA-JUI HSU and JOS E LUIS PINO, Agilent Technologies, Inc.
- Mapping Parameterized Cyclo-static Dataflow Graphs onto Configurable Hardware
