Rose, Jonathan - Department of Electrical and Computer Engineering, University of Toronto

• FPGA Routing Architecture: Segmentation and Buffering to Optimize Speed and Density
• Process technology advances tell us that the one-million gate Field-Programmable Gate Array (FPGA) will soon be here,
• IEEE JOURNAL OF SOLID-STATE CIRCUITS, VOL. 27, NO. 3, MARCH 1992 281 The Effect of Logic Block Architecture on FPGA
• Mixing Buffers and Pass Transistors in FPGA Routing Architectures Mike Sheng and Jonathan Rose
• Foundations and Trends R Electronic Design Automation
• A Novel and Efficient Routing Architecture for MultiFPGA Systems
• Transmogrifier2 Prototyping
• This paper describes the Transmogrifier-2, a second-generation multi-FPGA rapid prototyping system. The largest version of the system will comprise 16 boards that each contain two Altera 10K50 FPGAs, four I-Cube
• IEEE TRANSACTIONS ON VLSI SYSTEMS, VOL. XX, NO. Y, MONTH 1999 101 The Design of an SRAMBased
• Transmogrifier C Dave Galloway
• The tm2mon Program Dave Galloway
• Video-Rate Stereo Vision on Reconfigurable Hardware
• THE SUPERSMALL SOFT PROCESSOR James Robinson, Sam Vafaee, Jonathan Scobbie, Michael Ritche and Jonathan Rose
• IEEE TRANSACTIONS ON COMPUTER-AIDED DESIGN. VOL Y. NO IO. OCTOBtK IYYO 1085 Parallel Global Routing for
• VPR 5.0: FPGA CAD and Architecture Exploration Tools with Single-Driver Routing, Heterogeneity and Process
• FIELD PROGRAMMABLE LOGIC AND APPLICATIONS Measuring and utilising the correlation between
• As the logic capacity of FPGA increases, there has been a cor-responding increase in the variety of FPGA building blocks.
• As the logic capacity of Field-Programmable Gate Arrays (FPGAs) increases, they are being increasingly used to implement
• As the logic capacity of Field-Programmable Gate Arrays (FPGAs) increases, they are being increasingly
• Field-Programmable Gate Array Architectures and Algorithms Optimized
• IEEE TRANSACTIONS ON VLSI SYSTEMS, VOL. XX, NO. Y, MONTH 1999 101 The Design of an SRAMBased
• HUTTON ET. AL.: PARAMETERIZED GENERATION OF SYNTHETIC COMBINATIONAL BENCHMARK CIRCUITS 1 Characterization and Parameterized Generation of Synthetic
• Three factors are driving the demand for rapid FPGA compilation. First, as FPGAs have grown in logic capacity,
• Characterization and Parameterized Generation of Digital Circuits
• The Effect of LUT and Cluster Size on DeepSubmicron FPGA Performance and Density
• EVE: A CAD Tool for Manual Placement and Pipelining Assistance of FPGA Circuits
• The Memory/Logic Interface in FPGAs with Large Embedded Memory Arrays
• Using edif2blif Version 1.0 Paul Leventis
• Measuring the Gap between FPGAs and ASICs Ian Kuon and Jonathan Rose
• The Effect of LUT and Cluster Size on Deep-Submicron FPGA Performance and Density
• ROUTING ARCHITECTURE AND LAYOUT SYNTHESIS
• 620 IEEE TRANSACTIONS ON COMPUTER-AIDED DESIGN, VOL. 11, NO. 5, MAY 1992 A Detailed Router for Field-Programmable Gate
• This paper investigates the effect of the prefabricated routing track distribution on the areaefficiency of FPGAs.
• The Effect of Logic Block Complexity on Area of Programmable Gate Arrays
• Technology Mapping for Heterogeneous Jianshe He and Jonathan Rose
• A Synthesis Oriented Omniscient Manual Editor Tomasz S. Czajkowski and Jonathan Rose
• Nearest Neighbour Interconnect Architecture in Deep Submicron FPGAs Ajay Roopchansingh and Jonathan Rose
• We are motivated to determine the effect of pre-assign-ing signals to I/O pins in FPGAs because this situation
• IEEE TRANSACTIONS ON COMPUTER-AIDED DESIGN. VOL. 9. NO. 3, MARCH 1990 253 Temperature Measurement and Equilibrium Dynamics
• VPR: A New Packing, Placement and Routing Tool for FPGA Research1
• Characterization and Parameterized Random Generation of Digital Circuits Michael Huttony, J.P. Grossmanz, Jonathan Rose yy, and Derek Corneily
• Large circuits, whether they are arithmetic, digital signal processing, switching, or processors, typically contain a
• This paper describes the Transmogrifier2, a secondgeneration multiFPGA rapid prototyping system. The largest version of the system will comprise 16 boards that each contain two Altera 10K50 FPGAs, four ICube
• MultiFPGA systems (MFSs) are used as custom comput ing machines, logic emulators and rapid prototyping vehicles.
• In order to narrow the speed and density gap between FPGAs and MPGAs we propose the development of ``fami
• The Edward S. Rogers Sr. Dept of Electrical and Computer Engineering University of Toronto
• J. Becker, M. Platzner, S. Vernalde (Eds.): FPL 2004, LNCS 3203, pp. 1322, 2004. Springer-Verlag Berlin Heidelberg 2004
• While modern FPGAs often contain clusters of 4-input lookup tables and flip flops, little is known about good
• A Stochastic Model to Predict the Routability of FieldProgrammable Gate Arrays
• The demand for high-speed FPGA compilation tools has occurred for three reasons: first, as FPGA device capacity has grown, the
• Enhancing and Using an Automatic Design System for Creating FPGAs
• The Effect of Logic Block Complexity on Area of Programmable Gate Arrays
• Ultra-Fast Automatic Placement Yaska Sankar
• Technology Mapping and Architecture of Heterogeneous
• Architecture of FPGAs and CPLDs: A Tutorial Stephen Brown and Jonathan Rose
• WILTON ET AL: STRUCTURAL ANALYSIS AND GENERATION OF DIGITAL CIRCUITS WITH MEMORY 1 Structural Analysis and Generation of Synthetic
• PSACGen User's Manual (Version 1.0)
• Improving FPGA Routing Architectures Using Architecture and CAD Interactions
• The Microarchitecture of FPGA-Based Soft Processors Peter Yiannacouras, Jonathan Rose, and J. Gregory Steffan
• Memory/Logic Interconnect Flexibility in FPGAs with Large Embedded Memory Arrays
• While modern FPGAs often contain clusters of 4input lookup tables and flip flops, little is known about good
• Mixing Buffers and Pass Transistors in FPGA Routing Architectures Mike Sheng and Jonathan Rose
• Generation of Synthetic Sequential Benchmark Circuits \Lambda Michael Huttony, Jonathan Rosez and Derek Corneily
• Modeling Routing Demand for Early-Stage FPGA Architecture Development
• This paper describes the Transmogrifier-2, a second generation multi-FPGA system. The largest version of the system will
• In order to narrow the speed and density gap between FPGAs and MPGAs we propose the development of "fami-
• The Microarchitecture of FPGA-Based Soft Processors Peter Yiannacouras
• This paper examines the electrical design of FPGA inter-connect circuitry. We explore the circuit design of pass
• Enhancing the Area-Efficiency of FPGAs with Hard Circuits Using Shadow Clusters
• The demand for highspeed FPGA compilation tools has occurred for three reasons: first, as FPGA device capacity has grown, the
• Creating and Running Circuits for the TM2 Dave Galloway
• This paper describes the design and implementation of an SRAM-Programmable Field-Configurable Memory (FCM),
• VPR: A New Packing, Placement and Routing Tool for FPGA Research 1
• Automatic Generation of FPGA Routing Architectures from HighLevel Descriptions
• A High-Speed Ray Tracing Engine Built on a Field-Programmable System Joshua Fender
• 928 IEEE TRANSACTIONS ON COMPUTER-AIDED DESIGN OF INTEGRATED CIRCUITS AND SYSTEMS, VOL. 21, NO. 8, AUGUST 2002 Automatic Generation of Synthetic Sequential
• Architecture and Synthesis of Field-Programmable Gate Arrays with
• Design, Layout and Verification of an FPGA using Automated Tools
• WILTON ET AL: STRUCTURAL ANALYSIS AND GENERATION OF DIGITAL CIRCUITS WITH MEMORY 1 Structural Analysis and Generation of Synthetic
• Architectures and Algorithms for Field-Programmable Gate Arrays
• A VERILOG RTL SYNTHESIS TOOL FOR HETEROGENEOUS FPGAS Peter Jamieson, Jonathan Rose
• Architecture of Field-Programmable Gate Arrays
• Area and Delay Trade-offs in the Circuit and Architecture Design of FPGAs
• Improving the Area Efficiency of Heterogeneous FPGAs with Shadow Clusters
• Timing-Driven Placement for FPGAs Alexander (Sandy) Marquardt, Vaughn Betz, and Jonathan Rose1
• A Stochastic Model to Predict the Routability of Field-Programmable Gate Arrays
• Application-Specific Customization of Soft Processor Microarchitecture
• The TM2 Ports Package Dave Galloway
• MemorytoMemory Connection Structures in FPGAs with Embedded Memory Arrays
• This paper examines the electrical design of FPGA inter connect circuitry. We explore the circuit design of pass
• Mapping Multiplexers onto Hard Multipliers in Peter Jamieson and Jonathan Rose
• Hardware acceleration of a Monte Carlo simulation for photodynamic therapy treatment planning
• 266 IEEE TRANSACTIONS ON COMPUTER-AIDED DESIGN OF INTEGRATED CIRCUITS AND SYSTEMS, VOL. 26, NO. 2, FEBRUARY 2007 Exploration and Customization of
• IEEE TRANSACTIONS ON COMPUTER-AIDED DESIGN OF INTEGRATED CIRCUITS AND SYSTEMS, VOL. 26, NO. 2, FEBRUARY 2007 203 Measuring the Gap Between FPGAs and ASICs
• RAPID COMMUNICATIONS IN MASS SPECTROMETRY Rapid Commun. Mass Spectrom. 2005; 19: 833837
• SYNTHETIC CIRCUIT GENERATION USING CLUSTERING AND ITERATION
• 288 IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS, VOL. 12, NO. 3, MARCH 2004 The Effect of LUT and Cluster Size
• A Novel and Efficient Routing Architecture for Multi-FPGA Systems
• Effect of the Prefabricated Routing Track Distribution on FPGA Area-Efficiency
• ALL FIELD-PROGRAMMABLE GATE ar-rayscontainbothprogrammablelogicblocks
• Architecture of FPGAs and CPLDs: A Tutorial Stephen Brown and Jonathan Rose
• Synthesis Methods for Field Programmable Gate Arrays
• IEEE JOURNAL OF SOLIIXSTATE CIRCUITS, VOL. 25, NO. 5, OCTOBER 1990 1217 Architecture of Field-Programmable Gate
• IEEE TRANSACTIONS ON COMPUTER AIDED DESIGN, VOL 7, NO 3. MARCH IYXX 387 Parallel Standard Cell Placement Algorithms with
• DATA PARALLEL FPGA WORKLOADS: SOFTWARE VERSUS HARDWARE Peter Yiannacouras, J. Gregory Steffan, and Jonathan Rose
• GPU-accelerated Monte Carlo simulation for photodynamic therapy treatment planning
• FPGA-based Monte Carlo Computation of Light Absorption for Photodynamic Cancer Therapy
• Portable and Scalable FPGA-Based Acceleration of a Direct Linear System The Edward S. Rogers Sr. Dept. of
• Automated Transistor Sizing for FPGA Architecture Exploration
• Modeling Routing Demand for Early-Stage FPGA Architecture Development
• Architecting Hard Crossbars on FPGAs and Increasing their Area Efficiency with Shadow
• The Stratix II Logic and Routing Architecture David Lewis*, Elias Ahmed*, Gregg Baeckler, Vaughn Betz*, Mark Bourgeault*, David
• Hard vs. Soft: The Central Question of Pre-Fabricated Silicon Jonathan Rose
• Automatic Generation of FPGA Routing Architectures from High-Level Descriptions
• FPGA Routing Architecture: Segmentation and Buffering to Optimize Speed and Density
• In this paper, we investigate the speed and area-efficiency of FPGAs employing "logic clusters" containing multiple LUTs and
• Three factors are driving the demand for rapid FPGA compilation. First, as FPGAs have grown in logic capacity,
• Multi-FPGA systems (MFSs) are used as custom comput-ing machines, logic emulators and rapid prototyping vehicles.
• !"$#%'&( 0)132"#432"5768&9A@CBEDGFG6IHG&P3Q RSUTV7WXW!$WY `ab0FGc%"6
• This paper investigates the effect of the prefabricated routing track distribution on the area-efficiency of FPGAs.
• Multi-FPGA systems (MFSs) are used as custom comput-ing machines, logic emulators and rapid prototyping vehicles.
• Routing Algorithms and Architectures for Field-Programmable Gate Arrays
• Technology Mapping Lookup-Table Based
• A High-Speed Timing-Aware Router Jordan S. Swartz
• Cluster-Based Architecture, Timing-Driven Packing and
• Real-Time Face Detection on a Configurable Hardware Platform
• THE EFFECT OF LOGIC BLOCK GRANULARITY ON DEEP-SUBMICRON FPGA PERFORMANCE AND DENSITY
• NEAREST NEIGHBOUR INTERCONNECT ARCHITECTURE IN DEEP-SUBMICRON FPGAS
• EVE: A CAD Tool Providing Placement and Pipelining Assistance for
• SYNTHETIC CIRCUIT GENERATION USING CLUSTERING AND ITERATION
• Hardware Accelerated Protein Identification
• A SYNTHESIS ORIENTED OMNISCIENT MANUAL EDITOR FOR FPGA CIRCUIT DESIGN
• An FPGA-Based Hardware Development System with Multi-Gigabyte Memory Capacity And High Bandwidth
• Hardware Acceleration of a Monte Carlo Simulation for Photodynamic Therapy Treatment Planning
• A Hierarchical Description Language and Packing Algorithm for Heterogenous FPGAs
• Acceleration of Coevolution Detection for Predicting Protein Interactions
• Automatic Transistor-Level Design and Layout Placement of FPGA Logic and
• OPTIMIZATION OF TRANSISTOR-LEVEL FLOORPLANS FOR FIELD-PROGRAMMABLE GATE ARRAYS
• AUTOMATING TRANSISTOR RESIZING FIELD-PROGRAMMABLE GATE ARRAYS
• MultiFPGA systems (MFSs) are used as custom comput ing machines, logic emulators and rapid prototyping vehicles.
• TimingDriven Placement for FPGAs Alexander (Sandy) Marquardt, Vaughn Betz, and Jonathan Rose 1
• Advantages of Heterogeneous Logic Block Architectures for FPGAs \Lambda
• Effect of the Prefabricated Routing Track Distribution on FPGA AreaEfficiency
• A Parameterized Automatic Cache Generator for FPGAs Peter Yiannacouras and Jonathan Rose
• FPGA-Based Soft Vector Processors Peter Yiannacouras
• IEEE JOURNAL OF SOLID-STATE CIRCUITS, VOL. 26, NO. 3, MARCH 1991 277 Flexibility of Interconnection Structures for
• In this paper, we investigate the speed and areaefficiency of FPGAs employing ``logic clusters'' containing multiple LUTs and
• F I E L D -P R O G R A M M A B L E RECENTLY,the development of
• Portable and Scalable FPGA-Based Acceleration of a Direct Linear System Solver
• This paper describes the design and implementation of an SRAMProgrammable FieldConfigurable Memory (FCM),
• Architecture of Centralized FieldConfigurable Memory Steven J.E. Wilton, Jonathan Rose, and Zvonko G. Vranesic
• 462 IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS, VOL. 14, NO. 5, MAY 2006 Using Bus-Based Connections to Improve
• VESPA: Portable, Scalable, and Flexible FPGA-Based Vector Processors
• Architecture Description and Packing for Logic Blocks with Hierarchy, Modes and Complex Interconnect
• Comparing FPGA vs. Custom CMOS and the Impact on Processor Microarchitecture