- A Verilog Preprocessor for Representing Datapath Components
- The New DRAM Interfaces: SDRAM, RDRAM and
- MODERN DRAM ARCHITECTURES Brian Thomas Davis
- Researchers at the University of Michigan, in collaboration with their partners from Motorola and Cascade Design Automation,
- Copyright 1999 IEEE. Published in the Proceedings of the 26th International Symposium on Computer Architecture, May 24, 1999, in Atlanta GA, USA. Personal use of this material is per mitted. However, permission to reprint/republish this material for adve
- DDR2 and Low Latency Variants Brian Davis, Trevor Mudge Bruce Jacob, Vinodh Cuppu
- A Burst Scheduling Access Reordering Mechanism Jun Shao and Brian T. Davis
- Copyright 1999 IEEE. Published in the Proceedings of the 26th International Symposium on Computer Architecture, May 2-4, 1999, in Atlanta GA, USA. Personal use of this material is per-mitted. However, permission to reprint/republish this material for adv
- Prediction in Dynamic SDRAM Controller Policies
- photocredit PlayStation3'SabilitytoblaStdatabetweenchiPS
- Performance Evaluation of Exclusive Cache Hierarchies Ying Zheng Brian T. Davis Matthew Jordan
- This paper presents a simulation-based performance study of several of the new high-performance DRAM chitectures, each evaluated in a small system organization. These small-system organizations
- Researchers at the University of Michigan, in collaboration with their partners from Motorola and Cascade Design Automation,
- Brian Davis & Trevor Mudge University of Michigan, Ann Arbor
