- The FLASH multiprocessor efficiently integrates support for cachecoherent shared memory and highperformance message
- June 22, 1998 1 Cache-Coherent Distributed Shared Memory
- Active I/O Switches in System Area Networks Computer Systems Laboratory
- Integrated Memory Controllers with Parallel Coherence Streams
- SMTp: An Architecture for Next-generation Scalable Multi-threading Mainak Chaudhuri
- The Impact of Negative Acknowledgments in Shared Memory Scientific Applications
- Active Memory Techniques for ccNUMA Multiprocessors Daehyun Kim and Mainak Chaudhuri
- Active Memory Clusters: Efficient Multiprocessing on Commodity Clusters
- FLASH vs. (Simulated) FLASH: Closing the Simulation Loop
- Abstract--Scalable cache coherence protocols have become the key technology for creating moderate to large-scale shared-
- Given the limitations of bus-based multiprocessors, CC-NUMA is the scalable architecture of choice for shared-memory machines.
- 1 Introduction Two major trends in the digital design industry are the increase in
- Hardware/Software Codesign of the Stanford FLASH Multiprocessor Mark Heinrich, David Ofelt, Mark Horowitz, and John Hennessy
- Integrating Performance Monitoring and Communication in Parallel Computers
- A flexible communication mechanism is a desirable feature in multiprocessors because it allows support for multiple communi-
- Using Meta-level Compilation to Check FLASH Protocol Code Andy Chou, Benjamin Chelf, Dawson Engler
- Exploring Virtual Network Selection Algorithms in DSM Cache Coherence Protocols
- Computer Systems Laboratory Cornell University, Ithaca, NY 14853
- THE PERFORMANCE AND SCALABILITY OF DISTRIBUTED SHARED MEMORY CACHE COHERENCE PROTOCOLS
- Ocean Warning: Avoid Drowning Mark Heinrich
- Simplifying Active Memory Clusters by Leveraging Directory Protocol Threads
- HARDWARE/SOFTWARE CODESIGN OF PROCESSORS: CONCEPTS AND EXAMPLES
- Architectural Support for Uniprocessor and Multiprocessor Active Memory Systems
- Computer Systems Laboratory Cornell University, Ithaca, NY 14853
- Latency, Occupancy, and Bandwidth in DSM Multiprocessors: A Performance Evaluation
- The Effects of Latency and Occupancy in Distributed Shared Memory Multiprocessors
- The FLASH multiprocessor efficiently integrates support for cache-coherent shared memory and high-performance message
- Exploiting Active CMP-based Devices in System Area Computer Systems Laboratory
- Cache Coherence Protocol Design for Active Memory Systems
