Lee, Thomas H. - Department of Electrical Engineering, Stanford University

• Label-Free Impedance Biosensors: Opportunities and Challenges Jonathan S. Daniels,a, b
• Available online at www.sciencedirect.com Sensors and Actuators B 129 (2008) 7986
• A 2.125 Gbaud 1.6k Transimpedance Preamplifier in 0.5m CMOS
• A 5GHz, 32mW CMOS Frequency Synthesizer with an InjectionLocked
• A CMOS 4-PAM Multi-Gbps Serial Link Transceiver
• ISSCC 2003 / SESSION 4 / CLOCK RECOVERY AND BACKPLANE TRANSCEIVERS / PAPER 4.3 4.3 A Second-Order Semi-Digital Clock Recovery
• Superharmonic Injection Locked Oscillators as Low Power Frequency Hamid R. Rategh, Thomas H. Lee
• A 20Gb/s 0.13um CMOS Serial Link Transmitter Using an LC-PLL to Directly Drive the Output Multiplexer
• A 10Gb/s NRZ Receiver with Feedforward Equalizer and Glitch-Free Phase-Frequency Detector
• IEEE JOURNAL OF SOLID-STATE CIRCUITS, VOL. 33, NO. 12, DECEMBER 1998 2219 A 115-mW, 0.5-m CMOS GPS Receiver
• Simultaneous Measurement of Nonlinearity and Electrochemical Impedance for Protein Sensing Using Two-Tone Excitation
• Spills, Fills, and Kills An Architecture for Reducing Register-Memory Traffic
• Analysis and Optimization of Accumulation-Mode Varactor for RF ICs
• Ramin Farjad-Rad Kevin Yu, C.-K. Ken Yang, Bill Ellersick, Mark Horowitz, Thomas H. Lee
• 790 IEEE JOURNAL OF SOLID-STATE CIRCUITS, VOL. 34, NO. 6, JUNE 1999 Jitter and Phase Noise in Ring Oscillators
• Radio-Frequency Conversion and Synthesis (for a 115mW GPS Receiver)
• AN EFFICIENT I/O AND CLOCK RECOVERY DESIGN FOR TERABIT INTEGRATED CIRCUITS
• A 77GHz Monolithic IMPATT Transmitter in Standard CMOS Technology
• IEEE POWER ELECTRONICS LETTERS 1 A Constant-Frequency Method for Improving
• Buses and crossbars have tradition-ally served as the communication fabrics of
• Traveling Wave Spatial Quantized Analog-to-digital Conversion Mona Jarrahi, R. Fabian W. Pease, Thomas H. Lee
• Stanford University Concurrent VLSI Architecture Memo 124 Elastic Buffer Networks-on-Chip
• A Delay Model for Router Micro-architectures Li-Shiuan Peh William J. Dally
• A 5GHz, 32mW CMOS Frequency Synthesizer With an Injection Locked Frequency Divider
• SHAEFFER, ET AL. : FA 8.1 1 FA 8.1: A 115mW CMOS GPS Receiver
• 194 IEEE TRANSACTIONS ON PARALLEL AND DISTRIBUTED SYSTEMS, VOL. 3, NO. 2, MARCH 1992 Virtual-Channel Flow Control
• The BlackWidow High-Radix Clos Network Steve Scott
• http://smirc.stanford.edu/papers/CICC98p-ali.pdf Email: hajimiri@smirc.stanford.edu
• Tamara I. Ahrens & Thomas H. Lee Center for Integrated Systems
• 346 IEEE JOURNAL OF SOLID-STATE CIRCUITS, VOL. 35, NO. 3, MARCH 2000 Bandwidth Extension in CMOS with Optimized
• Locality-Preserving Randomized Oblivious Routing on Torus Networks
• EFFICIENT EMBEDDED COMPUTING A DISSERTATION
• In Proceedings of the 6th International Symposium on High-Performance Computer Architecture, Toulouse, France, January 10-12, 2000. pp. 73-84. Flit-Reservation Flow Control
• CMOS VCOs for Frequency Synthesis in Wireless Biotelemetry Rafael J. Betancourt Zamora and Thomas H. Lee
• Abstract--This paper presents a stochastic model for the observed signal of biosensors, a model that predicts the signal
• Theerachet Soorapanth and Thomas H. Lee Department of Electrical Engineering
• A serial link transmitter fabricated in the LSI 0.4-m CMOS process uses multilevel signaling (4-PAM) and a 3-tap pre-emphasis
• 326 IEEE JOURNAL OF SOLID-STATE CIRCUITS, VOL. 35, NO. 3, MARCH 2000 Oscillator Phase Noise: A Tutorial
• A 1.5mW, 200MHz CMOS VCO for Wireless Biotelemetry Rafael J. Betancourt-Zamora, Ali Hajimiri, Thomas H. Lee
• Figure 1: MDP Die Photo Figure 2: JMachine The JMachine: A Retrospective
• IEEE JOURNAL OF SOLID-STATE CIRCUITS, VOL. 35, NO. 11, NOVEMBER 2000 1591 Low-Power Area-Efficient High-Speed
• IEEE TRANSACTIONS ON COMPUTERS, VOL. 39, NO. 6, JUNE 1990 775 Performance Analysis of k-ary n-cube
• CMOS Operational Ampli er Design and Optimization via Geometric Programming Maria del Mar Hershenson, Stephen Boyd, Thomas H. Lee
• Stanford University Concurrent VLSI Architecture Memo 121 Stanford University
• Buffer and Delay Bounds in High Radix Interconnection Networks
• An Equalization Scheme for 10Gb s 4-PAM Signaling over Long Cables
• Microarchitecture of a High-Radix Router John Kim, William J. Dally, Brian Towles1
• 286 IEEE TRANSACTIONS ON SOLID STATE CIRCUITS, VOL. 35, NO. 2, FEBRUARY 2000 Correspondence________________________________________________________________________
• VLSI Architecture: Past, Present, and Future William J. Dally and Steve Lacy
• http://holst.stanford.edu/~CPYue yuechik@holst.stanford.edu This paper presents a novel on-chip inductor with a
• From T.H. Lee, The Design of CMOS Radio-Frequency Integrated Circuits A Nonlinear History of Radio 1998 Cambridge University Press Page 1 of 34
• THE DESIGN AND IMPLEMENTATION OF LOW-POWER CMOS RADIO RECEIVERS
• Ramin Farjad-Rad Center for Integrated Systems
• Stanford University, Stanford, CA 94305 Phase Noise in Multi-Gigahertz
• Globally Adaptive Load-Balanced Routing on Tori Arjun Singh, William J Dally, Brian Towles, and Amit K Gupta
• 2232 IEEE JOURNAL OF SOLID-STATE CIRCUITS, VOL. 33, NO. 12, DECEMBER 1998 Low-Power Dividerless Frequency
• IEEE JOURNAL OF SOLID-STATE CIRCUITS, VOL. 35, NO. 5, MAY 2000 765 A 5-GHz CMOS Wireless LAN Receiver Front End
• A 1.6 GHz 0.5 mW CMOS LC Low Phase Noise VCO Using Bond Wire Inductance
• A 115mW CMOS GPS Receiver Derek K. Shaeffer
• 780 IEEE JOURNAL ON SOLID-STATE CIRCUITS, VOL. 35, NO. 5, MAY 2000 A CMOS Frequency Synthesizer with
• This paper introduces a high-density linear capacitor structure with low bottom-plate parasitics. The density of such a struc-
• The Role of Custom Design in ASIC Chips William J. Dally and Andrew Chang
• Worst-case Traffic for Oblivious Routing Functions Brian Towles and William J. Dally
• IEEE/ACM TRANSACTIONS ON NETWORKING, VOL. 11, NO. 5, OCTOBER 2003 835 Guaranteed Scheduling for Switches
• CMOS Operational Ampli er Design and Optimization via Geometric
• A 1.5V, 1.5GHz CMOS Low Noise Amplifier Derek K. Shaeffer and Thomas H. Lee
• Route Packets, Not Wires: On-Chip Interconnection Networks William J. Dally and Brian Towles
• MEMORY HIERARCHY DESIGN FOR STREAM A DISSERTATION
• IEEE TRANSACTIONS ON ELECTRON DEVICES, VOL. 54, NO. 9, SEPTEMBER 2007 2369 Impact of a Process Variation on Nanowire and
• ARTICLE IN PRESS Bioluminescence regenerative cycle (BRC) system
• IEEE TRANSACTIONS ON MICROWAVE THEORY AND TECHNIQUES, VOL. 53, NO. 11, NOVEMBER 2005 3557 Monolithic Integrated Millimeter-Wave IMPATT
• * arjang@stanford.edu; phone 1 650 725-3658; fax 1 650 725-3383 Bioluminescence Regenerative Cycle (BRC) System for Nucleic Acid
• We implemented prescalers that can operate up to 2.8-GHz by exploiting the injection locking phenomena in differential
• -Introduction Interconnect Scaling in conventional CMOS
• 580 IEEE JOURNAL OF SOLID-STATE CIRCUITS, VOL. 34, NO. 5, MAY 1999 A 0.4-m CMOS 10-Gb/s 4-PAM
• IEEE JOURNAL OF SOLID-STATE CIRCUITS, VOL. 34, NO. 5, MAY 1999 717 Design Issues in CMOS Differential LC Oscillators
• A 5GHz, 1mW CMOS VoltageControlled Differential
• IEEE JOURNAL OF SOLID-STATE CIRCUITS, VOL. 34, NO. 6, JUNE 1999 813 Superharmonic Injection-Locked Frequency Dividers
• This paper presents a 12.4mW front-end for a 5GHz wire-less-LAN receiver fabricated in a 0.24-m CMOS technology.
• FA 8.1: A 115mW CMOS GPS Receiver D. Shaeffer, A. Shahani, S.S. Mohan, H. Samavati, H. Rategh
• Page 1 of 14 THE DESIGN OF NARROWBAND CMOS RF
• T. Lee, Paul G. Allen Center for Integrated Systems Recent Developments in CMOS RF Integrated Circuits
• 50-GHZ INTERCONNECT DESIGN IN STANDARD SILICON TECHNOLOGY Bendik Kleveland, Thomas H. Lee and S. Simon Wong
• Rafael J. Betancourt Zamora and Thomas H. Lee Stanford Microwave Integrated Circuits Laboratory
• IEEE JOURNAL OF SOLID-STATE CIRCUITS, VOL. 33, NO. 12, DECEMBER 1998 2035 Fractal Capacitors
• Modeling and Characterization of On-Chip Transformers Sunderarajan S. Mohan, C. Patrick Yue, Maria del Mar Hershenson, S. Simon Wong, and Thomas H. Lee
• SP 22.3: A 12mW Wide Dynamic Range CMOS Front-End for a Portable GPS Receiver
• IEEE JOURNAL OF SOLID-STATE CIRCUITS, VOL. 32, NO. 5, MAY 1997 745 A 1.5-V, 1.5-GHz CMOS Low Noise Amplifier
• Physical Modelling of Enhanced High-Frequency Drain and Gate Current Noise in Short-Channel MOSFETs
• Rafael J. Betancourt Zamora Ali Hajimiri, Thomas H. Lee
• CMOS RF: No Longer an Oxymoron Thomas H. Lee
• IEEE JOURNAL OF SOLID-STATE CIRCUITS, VOL. 32, NO. 12, DECEMBER 1997 2061 A 12-mW Wide Dynamic Range CMOS
• A 5GHz, 1mW CMOS Voltage Controlled Di erential Injection Locked Frequency Divider
• I2MTC 2008 IEEE Instrumentation and Measurement Technology Conference
• IEEE PHOTONICS TECHNOLOGY LETTERS, VOL. 20, NO. 7, APRIL 1, 2008 517 Wideband, Low Driving Voltage Traveling-Wave
• ISSCC 2007/1 SESSION 291 ANALOG AND POWER MANAGEMENT TECHNIQUES /29.6 29.6 A 3MHz Low-Voltage Buck Converter with The circuit of Figure 29.6.2 operates as follows: the drain-source
• 550 2007 IEEE International Solid-State Circuits Conference ISSCC 2007 / SESSION 30 / BUILDING BLOCKS FOR HIGH-SPEED TRANSCEIVERS / 30.7
• IEEE JOURNAL OF SOLID-STATE CIRCUITS, VOL. 35, NO. 5, MAY 2000 757 A 0.3-m CMOS 8-Gb/s 4-PAM Serial Link
• IEEE JOURNAL OF SOLID STATE CIRCUITS, VOL. 32, NO. 12, DEC 1997 1 A 12mW Wide Dynamic Range CMOS Front-End
• A CMOS Frequency Synthesizer with an Injection-Locked Frequency Divider for a 5 GHz
• A Fully-Integrated 5GHz CMOS Wireless-LAN Receiver
• Phase Noise in Oscillators Ali Hajimiri
• Modeling, Design and Optimization of On-Chip Inductors and Transformers
• THE DESIGN, MODELING AND OPTIMIZATION OF ON-CHIP INDUCTOR AND TRANSFORMER CIRCUITS
• 1ABabcdfghiejklStanford University Center for Integrated Systems
• Phase Noise in CMOS Differential LC Oscillators Ali Hajimiri, Thomas H. Lee
• Phase Noise in CMOS Ali Hajimiri
• Superharmonic Injection Locked Oscillators as Low Power
• A 12.4mW CMOS Front-End for a 5GHz Wireless-LAN Receiver
• COMPLETELY DC-FREE DIRECT SEQUENCE SPECTRUM SPREADING SCHEME FOR LOW POWER, LOW COST, DIRECT CONVERSION TRANSCEIVER
• T. Lee, Paul G. Allen Center for Integrated Systems Narrowband CMOS RF Low-Noise Amplifiers
• RF Linearity of Short-Channel MOSFETs Theerachet Soorapanth and Thomas H. Lee
• Tamara I. Ahrens Ali Hajimiri, Thomas H. Lee
• 1. ABSTRACT A new phase noise model was used to optimize a
• 1. ABSTRACT A 1.4-GHz LC voltage-controlled oscillator has
• SP 22.3: A 12m W W ide Dynam ic Range GPS Receiver Front-End
• Session FP 16: Paper 16.6 Fractal Capacitors
• 1999 IEEE International Solid-State Circuits Conference 0-7803-5129-0/99 IEEE 1999 MP 4.3 Monolithic CMOS Distributed Amplifier
• Department of Electrical Engineering Administration Mark Horowitz
• Course Requirements Total # of units: 45
• HIGH-RADIX INTERCONNECTION NETWORKS A DISSERTATION
• MEMORY AND CONTROL ORGANIZATIONS OF STREAM A DISSERTATION
• RESOURCE MANAGEMENT IN SINGLE-CHIP MULTIPROCESSORS
• SYNERGISTIC CACHING IN SINGLE-CHIP MULTIPROCESSORS
• DISTRIBUTED ROUTER FABRICS A DISSERTATION
• Flattened Butterfly : A Cost-Efficient Topology for High-Radix Networks
• Adaptive Channel Queue Routing on k-ary n-cubes Arjun Singh , William J Dally , Amit K Gupta , Brian Towles
• GOAL: A Load-Balanced Adaptive Routing Algorithm for Torus Networks Arjun Singh , William J Dally , Amit K Gupta , Brian Towles
• Scalable Opto-Electronic Network (SOENet) Amit K. Gupta
• IEEE TRANSACTIONS ON PARALLELANDDISTRIBUTED SYSTEMS,VOL. 4, NO. 4, APRIL 1993466 Short Notes
• Delay and Buffer Bounds in High Radix Interconnection Networks We apply recent results in queueing theory to propose a
• 1004 IEEE JOURNAL OF SOLID-STATE CIRCUITS, VOL. 40, NO. 4, APRIL 2005 A 20-Gb/s 0.13-m CMOS Serial Link Transmitter
• CMOS High-Speed I/Os --Present and Future M.-J. Edward Lee1
• 614 IEEE JOURNAL OF SOLID-STATE CIRCUITS, VOL. 38, NO. 4, APRIL 2003 Jitter Transfer Characteristics of Delay-Locked
• An 84-mW 4-Gb/s Clock and Data Recovery Circuit for Serial Link Applications M.-J. Edward Lee1,3, William J. Dally1,3, John W. Poulton2,3, Patrick Chiang1, and Stephen F. Greenwood1
• 390 IEEE ELECTRON DEVICE LETTERS, VOL. 21, NO. 8, AUGUST 2000 Distributed ESD Protection for High-Speed Integrated
• Appears in the Proceedings of the 38th International Symposium on Computer Architecture
• A 10-Gb/s serial link transmitter fabricated in the LSI 0.4-m CMOS process uses multilevel signaling (4-PAM) and a 3-tap pre-
• In Proceedings of the 7th International Symposium on High-Performance Computer Architecture, Jan. 22-24, 2001, Monterrey, Mexico, pp. 255-266. (Best Student Paper Award)
• IEEE JOURNAL OF SOLID-STATE CIRCUITS, VOL. 33, NO. 2, FEBRUARY 1998 179 A General Theory of Phase Noise
• Monolithic Chaotic Communications System P. Chiang, W. Dally, E. Lee
• Stanford University A 1.5V, 1.5GHz CMOS Low Noise Amplifier
• From Oxymoron to Mainstream: The Evolution and Future of RF Thomas H. Lee
• Analysis and Optimization of Accumulation-Mode Varactor for RF ICs Theerachet Soorapanth, C. Patrick Yue, Derek K. Shaeer, Thomas H. Lee, S. Simon Wong
• Optical switching based on high-speed phased array optical beam steering Mona Jarrahi,a
• Excessive High-Frequency Drain and Gate Current Noise in Short-Channel
• IEEE TRANSACTIONS ON ELECTRON DEVICES, VOL. 54, NO. 7, JULY 2007 1637 An Analytical Compact Circuit Model
• LOAD-BALANCED ROUTING IN INTERCONNECTION A DISSERTATION
• We propose a methodology that uses a new phase noise model to trade-off phase noise and power
• Rafael J. Betancourt Zamora Center for Integrated Systems
• QCD Calculations on the JMachine Robert Rippel
• 928 IEEE JOURNAL OF SOLID-STATE CIRCUITS, VOL. 33, NO. 6, JUNE 1998 Correspondence
• Comprehensive study of noise processes in electrode electrolyte interfaces Arjang Hassibi,a)
• http://holst.stanford.edu/~CPYue yuechik@holst.stanford.edu This paper presents a physical model for planar spiral
• Adaptive Routing in High-Radix Clos Network John Kim, William J. Dally, Dennis Abts
• IEEE JOURNAL OF SOLID-STATE CIRCUITS, VOL. 33, NO. 5, MAY 1998 743 On-Chip Spiral Inductors with Patterned
• Optimal Estimation of Gene Expression Levels in Microarrays
• Virtual-Channel Flow Controll William J. Dally
• 1ABabcdfghiejklStanford University Center for Integrated Systems
• 1804 IEEE JOURNAL OF SOLID-STATE CIRCUITS, VOL. 37, NO. 12, DECEMBER 2002 A Low-Power Multiplying DLL for Low-Jitter
• SHAEFFER AND LEE: A 1.5V, 1.5GHZ CMOS LOW NOISE AMPLIFIER 1 A 1.5V, 1.5GHz CMOS Low Noise Ampli er
• http://holst.stanford.edu/~CPYue yuechik@holst.stanford.edu On-Chip Spiral Inductors for
• Lateral IMPATT Diodes in Standard CMOS Technology Tala1Al-Attar, Michael D. Mulligan and Thomas H. Lee
• 1016 IEEE TRANSACTIONS ON COMPUTERS, VOL. 40, NO. 9, SEPTEMBER 1991 Express Cubes: Improving the Performance
• Digital Systems Engineering William J. Dally and John W. Poulton
• Modeling and Characterization of On-Chip Transformers
• A PROBABILISTIC MODEL FOR INHERENT NOISE AND SYSTEMATIC ERRORS OF MICROARRAYS
• MEMORY OPTIMIZATIONS OF EMBEDDED APPLICATIONS FOR ENERGY EFFICIENCY
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