John, Lizy Kurian - Department of Electrical and Computer Engineering, University of Texas at Austin

• 18 Characteristics of Texas Public Doctoral Programs Degree awarded
• Engineering A Continuing Reputation for Excellence
• 18 Characteristics of Texas Public Doctoral Programs Degree awarded
• Implementing Fault-Tolerant Services Using State Machines: Beyond Replication
• Hierarchical Computing: An Architecture for Ecient Transaction Juan Rubio and Lizy K. John
• Understanding the Branch Performance of Object Oriented R. Radhakrishnan, D. Tang and L. John
• 18 Characteristics of Texas Public Doctoral Programs Degree awarded
• 18 Characteristics of Texas Public Doctoral Programs Degree awarded
• 18 Characteristics of Texas Public Doctoral Programs Degree awarded
• An Efficient Test Set Embedding Scheme with Reduced Test-data Storage and Test Sequence Length Requirements for Scan-based Testing
• In the Proceedings of the 13th International Conference on Application-specific Systems, Architectures and Processors (ASAP 2002), July 2002 Implications of Programmable General Purpose Processors for
• Model Uncertainty in Discrete Event Systems \Lambda
• Modeling Stochastic Discrete Event Systems Using Probabilistic Languages 1
• Distributed Recovery with KOptimistic Logging YiMin Wang Om P. Damani Vijay K. Garg \Lambda
• Memory Latency Effects in Decoupled Architectures Lizyamma Kurian Paul T. Hulina and Lee D. Coraor
• Some Optimal Algorithms for Decomposed Partially Ordered Sets Vijay K. Garg
• 18 Characteristics of Texas Public Doctoral Programs Degree awarded
• Effective Use of Performance Monitoring Counters for Run-Time Prediction of Power
• Automatically Selecting Representative Traces for Simulation Based on Cluster Analysis of Instruction Address Hashes
• 18 Characteristics of Texas Public Doctoral Programs Degree awarded
• CRITICAL ISSUES REGARDING HPS, A HIGH PERFORMANCE MICROARCHITECTURE
• Load/Store Units Execution Core
• Control of Stochastic Discrete Event Systems: Synthesis \Lambda Ratnesh Kumar Vijay K. Garg
• Memory Chips with Adjustable Configurations Lizy Kurian John
• The Virtual Write Queue: Coordinating DRAM and Last-Level Cache Policies
• 18 Characteristics of Texas Public Doctoral Programs Degree awarded
• Distributed Computing manuscript No. (will be inserted by the editor)
• Formal Verification of a System-on-Chip Using Computation Slicing Alper Sen 1, Jayanta Bhadra 2, Vijay K. Garg 1 and Jacob A. Abraham 1
• Improving Memory Bank-Level Parallelism in the Presence of Prefetching
• Predicate Detection on Infinite Computations Anurag Agarwal Vijay K. Garg
• 18 Characteristics of Texas Public Doctoral Programs Degree awarded Completed 10/22/2010
• INTERNATIONAL Transfer Application Checklist DEADLINES: Summer/Fall: Feb 1 | Spring: October 1
• Quantifying the Effectiveness of MMX in Native Signal Processing Deependra Talla and Lizy K John
• Profile-assisted Compiler Support for Dynamic Predication in Diverge-Merge Processors
• Muhammad Faisal Iqbal mfiqbal@mail.utexas.edu
• CONTROL OF STOCHASTIC DISCRETE EVENT SYSTEMS: EXISTENCE Ratnesh Kumar, Vijay K. Garg 1
• A Quorumbased Distributed Channel Allocation Algorithm for Mobile Systems
• A Comparative Evaluation of Software Techniques to Hide Memory Latency Lizy Kurian John and Vinod Reddy
• Execution Characteristics of JustInTime Compilers Technical Report TR99071701
• Distributed Algorithms for Detecting Conjunctive Predicates Parallel and Distributed Systems Laboratory
• Today's high-performance processors face main-memory latencies on the order of
• Analyzing and Improving Clustering Based Sampling for Microprocessor Simulation
• Short-term production and synoptic influences on atmospheric 7
• November 18, 2003 Page 1 of 27 Basic Block Simulation Granularity, Basic Block Maps, and
• 18 Characteristics of Texas Public Doctoral Programs Degree awarded
• A Fusion-based Approach for Tolerating Faults in Finite State Machines
• Ravindra Nath Bhargava The Dissertation Committee for Ravindra Nath Bhargava
• 18 Characteristics of Texas Public Doctoral Programs Degree awarded
• VPC Prediction: Reducing the Cost of Indirect Branches via Hardware-Based Dynamic Devirtualization
• A Study of Cache Performance in Java Virtual Machines Anand Sunder Rajan, B.E., M.Sc
• Control of Event Separation Times in Discrete Event Systems
• Technical Report: Multislicing Vinit A. Ogale and Vijay K. Garg #
• Neeraj Mittal The Dissertation Committee for Neeraj Mittal
• 18 Characteristics of Texas Public Doctoral Programs Degree awarded
• Performance Benefits of Large Execution Atomic Units in Dynamically Scheduled Machines
• HPS, A NEW MICROARCHITECTURE: RATIONALE AND INTRODUCTION Yale N. Patt, Wen-mei Hwu, and Michael Shebanow
• Graduate School Planning Graduate & Professional School
• Is Compiling for Performance == Compiling for Power? Madhavi Valluri and Lizy John
• Understanding and Improving Operating System Effects in Control Flow Prediction
• 18 Characteristics of Texas Public Doctoral Programs Degree awarded
• 18 Characteristics of Texas Public Doctoral Programs Degree awarded
• 18 Characteristics of Texas Public Doctoral Programs Degree awarded
• Prefetch-Aware DRAM Controllers Chang Joo Lee Onur Mutlu Veynu Narasiman Yale N. Patt
• Rectangles are Better than Chains for Encoding Partially Ordered Neeraj Mittal
• Aashish Phansalkar Lizy Kurian John Department of Electrical and Computer Engineering
• Using Statistical Theory to Study Issues in Microprocessor Simulation Yue Luo and Lizy K. John
• Wrong Path Events: Exploiting Unusual and Illegal Program Behavior for Early Misprediction Detection and Recovery
• DRAM-Aware Prefetching and Cache Management Chang Joo Lee
• A Decoupled Translate Execute (DTE) Architecture to Improve Performance of Java Execution
• Program Balance and its Impact on High Performance RISC Architectures \Lambda Lizy Kurian John and Vinod Reddy
• An Online Algorithm Partition Posets into Chains # Anurag Agarwal
• Module Partitioning and Interlaced Data Placement Schemes to Reduce Conflicts in Interleaved Memories
• 18 Characteristics of Texas Public Doctoral Programs Degree awarded
• On Supervisory Control of Sequential Behaviors \Lambda Ratnesh Kumar
• Design of a Highly Reconfigurable Interconnect for Array Lizy Kurian and Daniel Brewer
• Finding Satisfying Global States: All for One and One Neeraj Mittal
• Address-Value Delta (AVD) Prediction: Increasing the Effectiveness of Runahead Execution by Exploiting Regular Memory Allocation Patterns
• Marvin L. Hackert Associate Dean of Graduate Studies
• Control of Stochastic Discrete Event Systems Modeled by Probabilistic Languages 1
• Modelling and Analysis of the Differencebit Cache Ashutosh Kulkarni, Navin Chander, Soumya Pillai and Lizy Kurian John
• A Novel Memory Bus Driver/Receiver Architecture for Higher Throughput Gregory E. Beers and Lizy K. John
• Improving the Parallelism and Concurrency in Decoupled Architectures
• Micro32 Fred Microarchitecture
• Detection of Strong Unstable Predicates in Distributed Programs 1 ,
• Los Angeles NY (Manhattan)
• OS-aware Tuning: Improving Instruction Cache Energy Efficiency on System Workloads
• Improving the Performance of Object-Oriented Languages with Dynamic Predication of Indirect Jumps
• Parallel Assertion Processing using Memory Snapshots
• 18 Characteristics of Texas Public Doctoral Programs Degree awarded
• 18 Characteristics of Texas Public Doctoral Programs Degree awarded
• Avoiding Store Misses to Fully Modified Cache Blocks Shiwen Hu Lizy John
• Design and VLSI Implementation of an Address Generation Coprocessor \Lambda
• Design and Performance Evaluation of a Cache Assist to implement Selective Caching
• Optimistic Recovery in Multithreaded Distributed Systems \Lambda Om P. Damani, Ashis Tarafdar Vijay K. Garg
• Microarchitecture Choices (Implementation of the VAX) Yale N. Patt
• Efficient Detection of Channel Predicates in Distributed Systems 1 V. K. Garg C. M. Chase Richard Kilgore J. Roger Mitchell
• A Performance Study of Modern Web Applications Ramesh Radhakrishnan and Lizy K. John
• Classification and Performance Evaluation of Instruction Buffering Techniques \Lambda
• Language Stability and Stabilizability of Discrete Event Dynamical Systems 1
• 18 Characteristics of Texas Public Doctoral Programs Degree awarded
• Automatic Testcase Synthesis and Performance Model Validation for High-Performance PowerPC Processors
• Data Marshaling for Multi-core Architectures M. Aater Suleman Onur Mutlu Jos A. Joao Khubaib Yale N. Patt
• 18 Characteristics of Texas Public Doctoral Programs Degree awarded
• **Advanced Labs include EE 321K, 440, 345L, 345S, 362L, 368L, 371C, 372L, and 374L.
• Investigating the Use of Cache as a Local Memory Lizy Kurian John, Raghuveer Reddy, Vijay Kammila and Peter Maurer
• Control of Discrete Event Systems Modeled with Deterministic Buchi
• A Nonblocking Recovery Algorithm for Causal Message Logging J. Roger Mitchell \Lambda Vijay K. Garg y
• Exploiting Fine-Grained Parallelism Through a Combination of Hardware and Software Techniques
• ESKIMO -Energy Savings using Semantic Knowledge of Inconsequential Memory Occupancy for DRAM subsystem
• OBSERVATION AND VERIFICATION OF SOFTWARE FOR DISTRIBUTED SYSTEMS
• 18 Characteristics of Texas Public Doctoral Programs Degree awarded
• 18 Characteristics of Texas Public Doctoral Programs Degree awarded
• Prefetch-Aware DRAM Controllers Chang Joo Lee Onur Mutlu Veynu Narasiman Yale N. Patt
• 18 Characteristics of Texas Public Doctoral Programs Degree awarded
• Exploiting Symmetry for Analysis of Distributed Systems 1 Vijay K. Garg 2
• Improving Server Performance on Transaction Processing Workloads by Enhanced Data Placement
• Distributed Computing manuscript No. (will be inserted by the editor)
• Improving the Performance of Object-Oriented Languages with Dynamic Predication of Indirect Jumps
• Generation, Validation and Analysis of SPEC CPU2006 Simulation Points Based on Branch,
• Using CompleteSystemSimulationto Characterize SPECjvm98 Benchmarks
• 2001 IEEE. Reprinted with permission from "Workload Characterization of Multithreaded Java Servers on Two PowerPC Processors" by Pattabi Seshadri and Alex Mericas, Proceedings of the Fourth Annual Workshop on
• MICROCODE AND THE PROTECTION OF INTELLECTUAL EFFORT Yale N. Patt and John K. Ahlsttrom +
• Performance and Energy Impact of Instruction-Level Value Predictor Filtering
• Execution Characteristics of Object Oriented Programs on the UltraSPARCII
• Observation of global properties in distributed systems Vijay K. Garg \Lambda
• Ramesh Radhakrishnan Microarchitectural Techniques to Enable
• Performance Model for a Prioritized MultipleBus Multiprocessor Lizy Kurian
• 18 Characteristics of Texas Public Doctoral ProgramsProgram Degree awarded
• 18 Characteristics of Texas Public Doctoral Programs Degree awarded
• 18 Characteristics of Texas Public Doctoral Programs Degree awarded
• Runahead Execution: An Alternative to Very Large Instruction Windows for Out-of-order Processors
• Technical Report : LCA-TR-020315 Implications of Programmable General Purpose
• Coordinated Control of Multiple Prefetchers in Multi-Core Systems
• Increasing the Instruction Fetch Rate via Multiple Branch Prediction and a Branch Address Cache
• 18 Characteristics of Texas Public Doctoral Programs Degree awarded
• 18 Characteristics of Texas Public Doctoral Programs Degree awarded
• Compiling Prolog Into Microcode: A Case Study Using the NCR/32-000
• Characterization of Java Applications at Bytecode and UltraSPARC Machine Code Levels
• Expressing and Detecting General Control Flow of Distributed Computations
• On Pipelining Dynamic Instruction Scheduling Logic Jared Stark y Mary D. Brown z Yale N. Patt z
• Efficient Detection of Restricted Classes of Global Predicates Craig M. Chase \Lambda Vijay K. Garg y
• Predictive Coordination of Multiple On-Chip Resources for Chip Multiprocessors
• 18 Characteristics of Texas Public Doctoral Programs Degree awarded
• On Reusing the Results of Pre-Executed Instructions in a Runahead Execution Processor
• Appears in the 19th International Conference on Supercomputing A NUCA Substrate for Flexible CMP Cache Sharing
• Design and VLSI Implementation of an Access Processor for a Decoupled Architecture
• Latency and Energy Aware Value Prediction for High-Frequency Processors
• A Performance Counter Based Workload Characterization on BlueGene/P
• A Study of Instruction Level Parallelism in Contemporary Computer Applications
• Marvin L. Hackert Associate Dean of Graduate Studies
• TSS: Applying Two-Stage Sampling in Micro-architecture Simulations
• Feedback-Directed Pipeline Parallelism M. Aater Suleman Moinuddin K. Qureshi Khubaib Yale N. Patt
• Timestamping Messages and Events in a Distributed System using Synchronous Communication
• Bank-aware Dynamic Cache Partitioning for Multicore Architectures Dimitris Kaseridis
• CAMPUS VISIT AWARD APPLICATION UNIVERSITY FELLOWSHIP PROGRAM
• VIJAY KUMAR GARG Cullen Trust for Higher Education Endowed Professor
• A Case Study of 3 Internet Benchmarks on 3 Superscalar Machines
• D. Kaeli and K. Sachs (Eds.): SPEC Benchmark Workshop 2009, LNCS 5419, pp. 5776, 2009. Springer-Verlag Berlin Heidelberg 2009
• Enumerating Global States of a Distributed Computation Vijay K. Garg
• Modeling Program Resource Demand Using Inherent Program Characteristics
• Prefetch-Aware Shared-Resource Management for Multi-Core Systems Eiman Ebrahimi Chang Joo Lee Onur Mutlu Yale N. Patt
• Reseeding-based Test Set Embedding with Reduced Test Sequences E. Kalligeros1, 2
• 18 Characteristics of Texas Public Doctoral Programs Degree awarded
• A Bandwidth-aware Memory-subsystem Resource Management using Non-invasive Resource Profilers for Large CMP Systems
• Performance Analysis of Multiple Threads/Cores Using the UltraSPARC T1
• A Bandwidth-aware Memory-subsystem Resource Management using Non-invasive Resource Profilers for Large CMP Systems
• Using Statistical Theory to Study Issues in Microprocessor Simulation Yue Luo and Lizy K. John
• Routine based OS-aware Microprocessor Resource Adaptation for Run-time Operating System Power Saving
• INTERNATIONAL Freshman Application Checklist DEADLINES: Summer/Fall: December 1 | Spring: October 1
• 18 Characteristics of Texas Public Doctoral Programs Degree awarded
• Bank-aware Dynamic Cache Partitioning for Multicore Architectures Dimitris Kaseridis
• 18 Characteristics of Texas Public Doctoral Programs Degree awarded
• Finding Satisfying Global States: All for One and One for Neeraj Mittal1, Alper Sen2, Vijay K. Garg2 , and Ranganath Atreya1
• Deconstructing and Improving Statistical Simulation in HLS Robert H. Bell Jr.
• 18 Characteristics of Texas Public Doctoral ProgramsProgram Degree awarded
• Analysis of Redundancy and Application Balance in the SPEC CPU2006 Benchmark Suite
• IEEE TRANSACTIONS ON AUTOMATIC CONTROL, VOL. XX, NO. Y, MONTH 1999 1 Supervisory Control of Realtime Discrete
• Monitoring Functions on Global States of Distributed Programs \Lambda Alexander I. Tomlinson Vijay K. Garg
• Detecting Temporal Logic Predicates in Distributed Programs Using Computation Slicing #
• An Algebra for Probabilistic Processes Vijay K. Garg 1
• VIJAY KUMAR GARG Cullen Trust for Higher Education Endowed Professor
• CAMPUS VISIT AWARD APPLICATION GRADUATE SCHOOL DIVERSITY MENTORING FELLOWSHIP PROGRAM
• Single Instruction Stream Parallelism Is Greater than Two Michael Butler, Tse-Yu Yeh, and Yale Patt Mitch Alsup, Hunter Scales, and Michael Shebanow
• Aashish Shreedhar Phansalkar The Dissertation Committee for Aashish Shreedhar Phansalkar certifies that this is
• Supervisory Control of Realtime Discrete Event Systems using Lattice Theory \Lambda
• Computation Slicing: Techniques and Theory Neeraj Mittal 1 and Vijay K. Garg 2?
• Performance Evaluation and Benchmarking of Native Signal Processing
• Hardware Support to Reduce Overhead in FineGrain Media Codes Deependra Talla, Lizy K. John, and Doug Burger
• Predicate Control for Active Debugging of Distributed Programs Ashis Tarafdar \Lambda
• Algorithmic Combinatorics based on Slicing Vijay K. Garg ?
• Value Based BTB Indexing for Indirect Jump Prediction Muhammad Umar Farooq, Lei Chen, and Lizy Kurian John
• Byeong Kil Lee The Dissertation Committee for Byeong Kil Lee
• 18 Characteristics of Texas Public Doctoral Programs Degree awarded
• 18 Characteristics of Texas Public Doctoral Programs Degree awarded
• An Investigation of the Performance of Various Dynamic Scheduling Michael Butler and Yale Patt
• IEEE TRANSACTIONS ON PARALLEL AND DISTRIBUTED SYSTEMS, VOL. 5, NO. 8, AUGUST 1994 823 Repeated Computation of Global Functions
• 18 Characteristics of Texas Public Doctoral Programs Degree awarded
• Debugging Distributed Programs Using Controlled Reexecution
• SelectFree Instruction Scheduling Logic Mary D. Brown y Jared Stark z Yale N. Patt y
• Detecting Temporal Logic Predicates on the HappenedBefore Model Alper Sen and Vijay K. Garg
• FORMULAS FOR CALCULATING SUPREMAL CONTROLLABLE AND NORMAL SUBLANGUAGES 1
• Timestamping Messages in Synchronous Computations Vijay K. Garg and Chakarat Skawratananond
• Distributed Resource Management Using Active Supervisory Predicate Control
• Consistency Conditions for Multi-Object Distributed Operations Neeraj Mittal Vijay K. Garg y
• 18 Characteristics of Texas Public Doctoral Programs Degree awarded
• Adaptive General Perfectly Periodic Scheduling Shailesh Patil and Vijay K. Garg
• Autocorrelation Analysis: A New and Improved Method for Measuring Branch Predictability
• Facilitating Superscalar Processing via a Combined Static/Dynamic Register Renaming Scheme
• High-performance processors exe-cute instructions out of program order to tol-
• Aaron Lee Smith The Dissertation Committee for Aaron Lee Smith
• Cache Filtering Techniques to Reduce the Negative Impact of Useless Speculative Memory References on Processor Performance
• Avoiding Store Misses to Fully Modified Cache Blocks This paper investigates a class of store misses that can
• 18 Characteristics of Texas Public Doctoral Programs Degree awarded
• 18 Characteristics of Texas Public Doctoral Programs Degree awarded
• Annex cache: a cache assist to implement selective caching L.K. Johna,*, T. Lia
• Performance Evaluation: Techniques, Tools and Benchmarks Author Info
• Synthesizing Memory-Level Parallelism Aware Miniature Clones for SPEC CPU2006 and
• Efficient Program Scheduling for Heterogeneous Multi-core Processors
• Enhanced Hierarchical Instruction Scheduling For Tiled Dataflow Architectures
• Simulation Points for SPEC CPU 2006 Arun A. Nair, Lizy K. John
• Energy-Aware Application Scheduling on a Heterogeneous Multi-core System
• Ciji Isen and Lizy John Electrical and Computer Engineering Department
• Analysis of Dynamic Power Management on Multi-Core W. Lloyd Bircher and Lizy K. John
• Complete System Power Estimation: A Trickle-Down Approach Based on Performance Events
• The DaCapo Benchmarks: Java Benchmarking Development and Analysis
• Analyzing and Improving Clustering Based Sampling for Microprocessor Simulation
• Runtime Identification of Microprocessor Energy Saving Opportunities
• Improved Automatic Testcase Synthesis for Performance Model Validation
• Low-Power, Low-Complexity Instruction Issue Using Compiler Assistance
• Analysis of the Execution of a Next Generation Application on Superscalar and Grid Processors
• On Load Latency in Low-Power Caches Soontae Kim, N. Vijaykrishnan, M. J. Irwin and L. K. John
• Run-time Modeling and Estimation of Operating System Power Consumption
• Rehashable BTB: An Adaptive Branch Target Buffer to Improve the Target Predictability of Java Code
• Modeling and Evaluation of Control Flow Prediction Schemes Using Complete System Simulation and Java Workloads
• Access Time and Energy Tradeoffs for Caches in High Frequency Microprocessors This research is supported in part by a State of Texas Advanced Technology Program grant and a UTSA Summer research grant.
• A binary CDMA bus is proposed as a communications interconnect for multiprocessor systems. The binary
• Workload Characterization of Multithreaded Java Servers Yue Luo and Lizy Kurian John
• Cost-effective Hardware Acceleration of Multimedia Applications Deependra Talla and Lizy K. John
• Evaluating Signal Processing and Multimedia Applications on SIMD, VLIW and Superscalar Architectures
• Execution Characteristics of Multimedia Applications on a Pentium II Processor
• An Evolutionary Computation Embedded IIR LMS Algorithm Deependra Talla1
• With the increasing effort towards exploiting the maxi-mum level of instruction level parallelism, modern micro-
• A NOVEL LOW POWER ENERGY RECOVERY FULL ADDER CELL
• Accurately Modeling Speculative Instruction Fetching in Trace-Driven Simulation
• CMP/CMT Scaling of SPECjbb2005 on UltraSPARC T1 Dimitris Kaseridis and Lizy K. John
• Cache Performance in Java Virtual Machines: A Study of Constituent Phases Anand S. Rajan
• Understanding the data memory behavior of benchmarks using Principal Components Analysis
• Memory Access and Computational Behavior of MP3 Encoding
• Physical Address Execution Core
• William Lloyd Bircher Dissertation Committee for William Lloyd Bircher
• Ajay Manohar Joshi The Dissertation Committee for Ajay Manohar Joshi certifies that this is the
• Robert Henry Bell, Jr. The Dissertation Committee for Robert Henry Bell, Jr. Certifies that this is the
• The Dissertation Committee for Shiwen Hu Certifies that this is the approved version of the following dissertation
• The Dissertation Committee for Tao Li Certifies that this is the approved version of the following dissertation
• Measuring Benchmark Similarity Using Inherent Program Characteristics Ajay Joshi
• Experiments in Automatic Benchmark Synthesis Robert H. Bell, Jr. Lizy K. John
• More on finding a Single Number to indicate Overall Performance of a Benchmark Suite
• LCA TECHNICAL REPORT TR-030827-01
• The Role of Return Value Prediction in Exploiting Speculative Method-Level Parallelism
• Value Prediction Design for High-Frequency Microprocessors Ravi Bhargava and Lizy K. John
• Exploiting Instruction Reuse to Enhance Microprocessor Simulation Ravi Bhargava, Lizy K. John, Francisco Matus
• The Laboratory for Computer Archi-tecture (LCA) is a research group
• Superscalar Comp. Arch. ECD Fall 2006, The University of Texas at Austin
• UT-ECE ranks among the best engineering programs in the world. With nearly 200
• Los Angeles NY (Manhattan)
• B S E E , E l e c t r i c a l a n d C o m p u t e r E n g i n e e r i n gB S E E , E l e c t r i c a l a n d C o m p u t e r E n g i n e e r i n g C u r r i c uC u r r i c u l u ml u m
• Electromagnetic Engineering
• REGISTRATION FLOW CHART Policies & Procedures for graduate students to get their advising bar cleared and to register for classes.
• REGISTRATION FLOW CHART Policies & Procedures for graduate students to get their advising bar cleared and to register for classes.
• Laboratory for Computer Architecture 6/21/2010 The Virtual Write Queue: Coordinating DRAM
• Electrical and Computer Engineering Revised December 06, 2010 THE UNIVERSITY OF TEXAS AT AUSTIN
• Low Power Set-Associative Cache with Single-Cycle Partial Tag Comparison
• Future Generation Supercomputers II: A Paradigm for Cluster Architecture N.Venkateswaran, Deepak Srinivasan, Madhavan Manivannan, TP Ramnath Sai Sagar
• Memory Efficient Application Execution In Venkateswaran N, Arvind M, Karthik C, Karthik G, Vishwanath V and Viswanath K
• HIERARCHICAL MULTIHOST BASED OPERATING SYSTEM FOR SIMULTANEOUS MULTIPLE APPLICATION
• EMULATING IBM BLUEGENE ON A LINUX MPI CLUSTER
• NpBench: A Benchmark Suite for Control plane and Data plane Applications for Network Processors
• Workload Characterization of Multithreaded Java Servers on Two PowerPC Pattabi Seshadri
• Understanding and Improving Operating System Effects in Control Flow Prediction
• Using Complete Machine Simulation for Software Power Estimation: The SoftWatt Approach
• Architectural Techniques for Improving Fine-grain Multiprocessor Performance
• FastMATHTM Overview October 28, 2002
• Towards Pervasive Parallelism Kunle Olukotun
• Diverge-Merge Processor (DMP): Dynamic Predicated Execution of Complex Control-Flow Graphs Based on Frequently Executed Paths
• Wish Branches: Combining Conditional Branching and Predication for Adaptive Predicated Execution
• Two-Level Adaptive Training Branch Predict ion Tse-Yu Yeh and Yale N. Patt
• Microarchitectural Support for Precomputation Microthreads Robert S. Chappell
• Difficult-Path Branch Prediction Using Subordinate Microthreads
• Flexible Reference-Counting-Based Hardware Acceleration for Garbage Collection
• Accelerating Critical Section Execution with Asymmetric Multi-Core Architectures
• Techniques for Bandwidth-Efficient Prefetching of Linked Data Structures in Hybrid Prefetching Systems
• An Analysis of the Performance Impact of Wrong-Path Memory References on Out-of-
• Microarchitecture-Based Introspection: A Technique for Transient-Fault Tolerance in Microprocessors
• Techniques for Efficient Processing in Runahead Execution Engines Onur Mutlu Hyesoon Kim Yale N. Patt
• The V-Way Cache : Demand-Based Associativity via Global Replacement Moinuddin K. Qureshi David Thompson Yale N. Patt
• Understanding The Effects of Wrong-Path Memory References on Processor Performance
• Partitioned First-Level Cache Design for Clustered Microarchitectures
• A Comparative Performance Evaluation of Various State Maintenance Mechanisms
• A Comprehensive Instruction Fetch Mechanism for a Processor Supporting Speculative Execution
• The Effect of Iteai Data Cache Behavior on the Performance Micmarchitectmre that Supports Dynamic Scheduling
• A High Performance Prolog Processor with Multiple Function Units Ashok Singhal
• Hierarchical Registers for Scientific Computers John A. Swensen
• Fast Temporary Storage for Serial and Parallel Execution John Swensen
• On Tuning the Microarchitecture of an HPS Implementation of the VAX James E. Wilson, Steve Melvin, Michael Shebanow, Wen-mei Hwu, and Yale N. Patt
• SPAM: A Microcode Based Tool for Tracing Operating System Events Stephen W. Melvin
• The Implementation of Prolog via VAX 8600 Microcode JeffGee,StephenW.Melvin, YaleN. Patt
• An Asymmetric Multi-core Architecture for Accelerating Critical Sections M. Aater Suleman Onur Mutlu Moinuddin Qureshi Yale N. Patt
• The Weighted Byzantine Agreement Problem Vijay K. Garg and John Bridgman
• Modeling and Analyzing Periodic Distributed Computations
• An Efficient Decentralized Algorithm for the Distributed Trigger Counting Problem
• A Fusion-based Approach for Tolerating Faults in Finite State Machines
• Detecting Temporal Logic Predicates on Distributed Computations
• Fusible Data Structures for Fault-Tolerance Vijay K. Garg
• COORDINATED ENERGY CONSERVATION IN AD HOC NETWORKS Selma Ikiz, Vinit A. Ogale and Vijay K. Garg
• Detecting Temporal Logic Predicates in Distributed Programs Using Computation Slicing
• On Checking Whether a Predicate Definitely Holds Alper Sen and Vijay K. Garg
• Detecting Temporal Logic Predicates on the Happened-Before Model Alper Sen and Vijay K. Garg
• On Detecting Global Predicates in Distributed Computations Neeraj Mittal
• On Slicing a Distributed Computation Vijay K. Garg
• Debugging Distributed Programs Using Controlled Re-execution
• An E cient Deterministic Algorithm for the Resource Discovery Problem
• JOURNAL OF PARALLEL AND DISTRIBUTED COMPUTING 45, 134147 (1997) ARTICLE NO. PC971374
• technical contributions ))];V'Tl!7;i'~E.~];Cli,.h':"+L. ~%Nf>....Y!7:',];~777; ];N ,r' f:~,.>t..,+..,........ l...
• A Fusion-based Approach for Handling Multiple Faults in Distributed Systems
• Meet-and join-closure of CTL operators Sujatha Kashyap and Vijay K. Garg
• State space reduction using Predicate Filters Sujatha Kashyap and Vijay K. Garg
• COORDINATED ENERGY CONSERVATION IN AD HOC NETWORKS Selma Ikiz, Vinit A. Ogale and Vijay K. Garg
• Application TRANSFER Checklist DEADLINES: Summer/Fall: March 1 | Spring: October 1
• Graduate School 0407 FINAL CERTIFICATION OF COMPLETION OF DEGREE REQUIREMENTS
• New UT Undergraduates Total UT Enrollment ADMISSION STATISTICS Undergraduate 38,420 75.0%
• 18 Characteristics of Texas Public Doctoral Programs Degree awarded
• 18 Characteristics of Texas Public Doctoral Programs Degree awarded
• 18 Characteristics of Texas Public Doctoral Programs Degree awarded
• 18 Characteristics of Texas Public Doctoral Programs Degree awarded
• 18 Characteristics of Texas Public Doctoral Programs Degree awarded
• 18 Characteristics of Texas Public Doctoral Programs Degree awarded
• 18 Characteristics of Texas Public Doctoral Programs Degree awarded Completed 10/24/2010
• 18 Characteristics of Texas Public Doctoral Programs Degree awarded
• 18 Characteristics of Texas Public Doctoral Programs Degree awarded
• 18 Characteristics of Texas Public Doctoral Programs Degree awarded
• 18 Characteristics of Texas Public Doctoral Programs Degree awarded
• 18 Characteristics of Texas Public Doctoral Programs Degree awarded
• 18 Characteristics of Texas Public Doctoral Programs Degree awarded
• 18 Characteristics of Texas Public Doctoral Programs Degree awarded
• 18 Characteristics of Texas Public Doctoral Programs Degree awarded
• 18 Characteristics of Texas Public Doctoral Programs Degree awarded
• 18 Characteristics of Texas Public Doctoral Programs Degree awarded
• 18 Characteristics of Texas Public Doctoral Programs Degree awarded
• 18 Characteristics of Texas Public Doctoral Programs Degree awarded
• 18 Characteristics of Texas Public Doctoral Programs Degree awarded
• 18 Characteristics of Texas Public Doctoral Programs Degree awarded
• 18 Characteristics of Texas Public Doctoral Programs Degree awarded
• 18 Characteristics of Texas Public Doctoral Programs Degree awarded
• 18 Characteristics of Texas Public Doctoral Programs Degree awarded
• Keeton/26th Keeton/26th
• UT Graduate & Professional School Fair 2010 Academy of Art University
• HARRINGTON CAMPUS VISIT AWARD APPLICATION HARRINGTON GRADUATE FELLOWSHIP PROGRAM
• DRAM-Aware Last-Level Cache Writeback: Reducing Write-Caused Interference in Memory Systems
• Efficient Power Analysis using Synthetic Testcases Robert H. Bell, Jr.
• Java Runtime Systems: Characterization and Architectural Implications
• Use ECP, not ECC, for Hard Failures in Resistive Memories Stuart Schechter, Gabriel H. Loh
• Strategies for Mapping Dataflow Blocks to Distributed Hardware Behnam Robatmili, Katherine E. Coons
• Appears in the Proceedings of the Annual IEEE/ACM International Symposium on Microarchitecture Merging Head and Tail Duplication for Convergent Hyperblock Formation
• Appears in the International Conference on Architectural Support for Programming Languages and Operating Systems A Spatial Path Scheduling Algorithm for EDGE Architectures
• 24 OL-4637-03 Making Conference Calls
• Vikas Agarwal The Dissertation Committee for Vikas Agarwal
• High Performance Low Power Single Chip Reconfigurable Supercomputer for High-end
• Hardware Support for Large Atomic Units in Dynamically Scheduled Machines
• Cache Performance in Java Virtual Machines: A Study of Constituent Phases Anand S. Rajan, Juan Rubio and Lizy K. John
• 18 Characteristics of Texas Public Doctoral Programs Degree awarded
• Simulating Java Commercial Throughput Workload: A Case Study Yue Luo and Lizy K. John
• Fast Tree-Structured Computations and Memory Hierarchies
• Exploiting Predicate Structure For Efficient Reachability Sujatha Kashyap
• Compiler Controlled Speculation for Power Aware ILP Extraction in Dataflow Architectures
• This paper quantifies the performance of typical func-tional unit interface designs in single-chip systems. We
• Performance Evaluation of Configurable Hardware Features on the AMDK5
• Optimal Supervisory Control of Discrete Event Dynamical Systems 1;2
• Software Fault Tolerance of Concurrent Programs Using Controlled Reexecution ?
• Feedback Driven Pipelining M. Aater Suleman Moinuddin Qureshi Khubaib Yale N. Patt
• Dynamic Predication of Indirect Jumps Jose A. Joao*, Onur Mutlu, Hyesoon Kim*, and Yale N. Patt*
• 0018-9162/03/$17.00 2003 IEEE34 Computer Benchmarking
• Improving Dynamic Cluster Assignment for Clustered Trace Cache Processors
• A Microcode-Based Environment for Non-Invasive Performance Analysis Stephen W. Melvin
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• ehirpxf: A Cost-Effective Way to Implement Full Map Directory-Based
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• Distributed Maintenance of a Spanning Tree using Labeled Tree Encoding
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• On SelfStabilizing Systems: An Approach to the Specification and Design of Fault
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• Mapping of Applications to Heterogeneous Multi-cores Based on Micro-architecture Independent Characteristics
• MediaBreeze: A Decoupled Architecture for Accelerating Multimedia Applications
• The Effects of MemoryAccess Ordering on MultipleIssue Uniprocessor Performance \Lambda
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• Exploiting SIMD Parallelism in DSP and Multimedia Algorithms Using the AltiVec tm Technology Huy Nguyen and Lizy Kurian John*
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• Formal Verification of a SystemonChip Using Computation Slicing Alper Sen 1 , Jayanta Bhadra 2 , Vijay K. Garg 1 and Jacob A. Abraham 1
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• The Role of Return Value Prediction in Exploiting Speculative Method-Level Parallelism
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• Distributed predicate detection in a faulty environment Vijay K. Garg \Lambda J. Roger Mitchell y
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• Applications of Lattice Theory to Distributed Vijay K. Garg
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• Producing short counterexamples using "crucial events" Sujatha Kashyap1
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