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- Stream Programming on the Blackfin Architecture Michael G. Benjamin and David Kaeli
- A Field Analysis of System-level Effects of Soft Errors Occurring in Microprocessors used in Information Systems
- Int. J. High Performance Computing and Networking, Vol. 1, Nos. 1/2/3 , 2004 85 Copyright 2004 Inderscience Enterprises Ltd.
- A Study of Dynamic Branch Prediction for SHARC DSPs Suleyman Sair
- Performance Characterization of SPEC CPU2006 Integer Benchmarks on x86-64 Architecture
- Architecture-Aware Optimization Targeting Multithreaded Stream Computing
- Exploring the Multiple-GPU Design Space Dana Schaa and David Kaeli
- Analytic Models of Workload Behavior and Pipeline Performance Mark S. Squillante
- Accurate Simulation and Evaluation of Code Reordering John Kalamatianos & David R. Kaeli
- Load Balancing using Grid-based Peer-to-Peer Parallel I/O Yijian Wang and David Kaeli
- Characterization of File I/O Activity for SPEC CPU2006
- A Benchmark Suite for Behavior-Based Security Mechanisms This paper presents a benchmark suite for evaluating
- cm212-02 ACM-TRANSACTION June 7, 2004 19:28 Removing Communications in Clustered
- Eliminating Microarchitectural Dependency from Architectural Vulnerability Vilas Sridharan and David R. Kaeli
- Electromagnetics Computations Using the MPI Parallel Implementation of the Steepest Descent Fast Multipole Method (SDFMM)
- Vulnerability Analysis of L2 Cache Elements to Single Event Upsets Hossein Asadi Vilas Sridharan Mehdi B. Tahoori David Kaeli
- Performance analysis on a CC-NUMA prototype D. R. Kaeli
- Improving the Accuracy of HistoryBased Branch Prediction David R. Kaeli and Philip G. Emma
- Cache Analysis in a Multiprocess Environment Using Execution Driven
- Reliability in the Shadow of Long-Stall Instructions Vilas Sridharan David Kaeli
- Hunting Trojan Horses Micha Moffie
- Parameter Value Characterization of Windows NT-based Applications John Kalamatianos Ronnie Chaiken
- A STUDY of LOOP UNROLLING for VLIWBASED DSP PROCESSORS
- VLSI Design in the 3rd Dimension Stephen Strickland
- Power Aware External Bus Arbitration for System-on-a-Chip Embedded Systems
- Subsequence Matching on Structured Time Series Data Northeastern University
- Characterizing the Relationship between ILU-type Preconditioners and the Storage Hierarchy
- Operating System Impact on TraceDriven Simulation Jason Casmira
- Studying the Performance of the FX!32 Binary Translation System Paul J. Drongowski
- Predicting Indirect Branches via Data Compression John Kalamatianos & David R. Kaeli
- Addressing a Workload Characterization Study to the Design of Consistency Protocols
- Profile-Guided File Partitioning on Beowulf Clusters Yijian Wang and David Kaeli
- Accelerating the Local Outlier Factor Algorithm on a GPU for Intrusion Detection Systems
- Localized Message Passing Structure for High Speed Ethernet Packet Switching
- Resource-Conscious Optimization of Cryptographic Algorithms on an Embedded Architecture
- Exploiting Temporal Locality in Drowsy Cache Policies Salvador Petit, Julio Sahuquillo, Jose M. Such
- Design of a Subsurface Sensing and Imaging Image and Sensor Data Database System
- Reliability Tradeoffs in Design of Cache Memories Hossein Asadi, Vilas Sridharan, Mehdi B. Tahoori, David Kaeli
- An adjustable linear time parallel algorithm for maximum weight bipartite matching
- Modeling Cache Pollution Jason P. Casmira
- Procedure Mapping Using Static Call Graph Estimation Amir Hooshang Hashemi David R. Kaeli Brad Calder
- Interactive Deformable Registration Visualization and Analysis of 4D Computed
- Performance Characterization of SPEC CPU2006 Integer Benchmarks on x86-64 Architecture
- Acceleration of Maximum Likelihood Estimation for Tomosynthesis Mammography
- At Northeastern University we are building a number of courses upon a common embedded systems platform. The goal
- Boston Area Computer Architecture Research Workshop January 30, 2004
- 2714 IEEE TRANSACTIONS ON NUCLEAR SCIENCE, VOL. 54, NO. 6, DECEMBER 2007 Soft Error Susceptibility Analysis of SRAM-Based
- An M/G/1 Queue Model for Multiple Applications on Storage Area Networks Emmanuel Arzuaga and David R. Kaeli
- A Multinomial Clustering Model for Fast Simulation of Computer Architecture Designs
- A Reliable Return Address Stack: Microarchitectural Features to Defeat Stack Smashing
- OperatingSystem Level Tracing Tools for the DEC AXP Architecture Jason P. Casmira
- A Taxonomy to Enable Error Recovery and Correction in Software Vilas Sridharan
- Software Transactional Memory for Multicore Embedded Systems
- MULTI GPU IMPLEMENTATION OF ITERATIVE TOMOGRAPHIC RECONSTRUCTION Byunghyun Jang, David Kaeli
- Characterizing the relationship between ILU-type preconditioners and the storage Co-authored by
- Analytic Models of Workload Behavior and Pipeline Performance Mark S. Squillante
- Published in the Proceedings of HPCA4, Feb 14, 1998 in Las Vegas, Nevada. Temporalbased Procedure Reordering for Improved Instruction Cache
- Accurate Simulation and Evaluation of Code Reordering John Kalamatianos & David R. Kaeli
- MULTI GPU IMPLEMENTATION OF ITERATIVE TOMOGRAPHIC RECONSTRUCTION Byunghyun Jang, David Kaeli
- Heterogeneous Clustered VLIW Microarchitectures lex Alet1
- Case Study: Soft Error Rate Analysis in Storage Systems Brian Mullins, Hossein Asadi, Mehdi B. Tahoori, David Kaeli
- Exploring Novel Parallelization Technologies for 3-D Imaging Applications Diego Rivera Dana Schaa Micha Moffie
- External Memory Page Remapping for Embedded Multimedia Analog Devices Inc.
- Balancing Performance and Reliability in the Memory Hierarchy Ghazanfar-Hossein Asadi Vilas Sridharan Mehdi B. Tahoori David Kaeli
- Demystifying On-the-Fly Spill Code Alex Alet`a
- Developing Energy-Aware Strategies for the Blackfin Processor Steven VanderSanden, David R. Kaeli Giuseppe Olivadoti, Richard Gentile
- A Database System to Advance Subsurface Sensing and Imaging
- PROFILE-BASED CHARACTERIZATION AND TUNING FOR SUBSURFACE SENSING AND IMAGING
- Realizing High IPC Using Time-Tagged Resource-Flow Augustus Uht1
- Path-based Hardware Loop Prediction Marcos R. de Alba
- Exploiting Pseudo-schedules to Guide Data Dependence Graph Partitioning
- Introduction to the Special Issue on High Performance Memory Systems
- 0018-9162/00/$10.00 2000 IEEE40 Computer Welcome to the
- Using Cache Line Coloring to Perform Aggressive Procedure Hakan Aydin
- A Binary Instrumentation Tool for the Blackfin Processor Enqiang Sun
- The Effect of Input Data on Program Vulnerability Vilas Sridharan and David R. Kaeli
- Accelerating Phase Unwrapping and Affine Transformations for Optical Quadrature Microscopy using
- A Field Failure Analysis of Microprocessors used in Information Systems Soft errors due to cosmic particles are a growing
- Performance Evaluation of Virtual Appliances Zhaoqian Chen and David Kaeli
- Quantifying Software Vulnerability Vilas Sridharan
- Stream Image Processing on a Dual-Core Embedded Michael G. Benjamin and David Kaeli
- A Code Layout Framework for Embedded Processors with Configurable Memory Hierarchy
- An Automated Instruction Level DSP Energy Profiling Framework Seth Molloy David Kaeli
- ASM --Application Security Monitor Micha Moffie and David Kaeli
- Runtime Predictability of Loops Marcos R. de Alba
- Technical Report TR-01 January 2006
- 1/30/2004 1 Reliable Return Address Stack
- Whitepaper on Characterizing NAV Execution Overhead D. Uluski, M. Moffie and D. Kaeli
- Characterizing Antivirus Workload Execution Derek Uluski, Micha Moffie and David Kaeli
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- The CenSSIS Image Database Huanmei Wu, Becky Norum, Judith Newmark, Betty Salzberg,
- Quantifying Load Imbalance on Virtualized Enterprise Emmanuel Arzuaga
- Use of an Embedded Configurable Memory for Stream Image Processing
- Reducing Data Cache Susceptibility to Soft Errors Hossein Asadi, Vilas Sridharan, Mehdi B. Tahoori, David Kaeli
- Case Study: Soft Error Rate Analysis in Storage Systems Brian Mullins, Hossein Asadi, Mehdi B. Tahoori, David Kaeli
- To appear at the ACM SIGPLAN Conference on Programming Language Design and Implementation, June, 1997 Efficient Procedure Mapping Using Cache Line Coloring
- Data Transformations Enabling Loop Vectorization on Multithreaded Data Parallel Architectures
- AGAMOS: A Graph-Based Approach to Modulo Scheduling for Clustered Microarchitectures
- Guest Editors' Introduction Erik R. Altman, David Kaeli, Yaron Sheffer