- Multi-objective Circuit Partitioning for Cutsize and Path-Based Delay Minimization Cristinel Ababei* Navaratnasothie Selvakkumaran** Kia Bazargan* George Karypis**
- Placement Method Targeting Predictability Robustness and Performance
- Thermal-Aware Floorplanning for Task Migration Enabled Active Sub-threshold Leakage Reduction
- Fast Timing-driven Partitioning-based Placement for Island Style FPGAs
- Three-dimensional Place and Route for FPGAs Cristinel Ababei Hushrav Mogal Kia Bazargan
- STATISTICAL GENERIC AND CHIP-SPECIFIC SKEW ASSIGNMENT FOR IMPROVING TIMING YIELD OF FPGAS
- Timing Minimization by Statistical Timing hMetis-based Partitioning Cristinel Ababei Kia Bazargan
- Abstract--We present timing-driven partitioning and simulated annealing based placement algorithms together with a
- FAST FLOORPLANNING FOR EFFECTIVE PREDICTION AND CONSTRUCTION K. Bazargan
- A Reconfigurable FPGA-Based Readback Signal Generator For Hard-Drive Read Channel Simulator
- HARP: Hard-wired Routing Pattern FPGAs Satish Sivaswamy
- Using Randomization to Cope with Circuit Uncertainty
- FAST HIERARCHICAL FLOORPLANNING WITH CONGESTION AND TIMING CONTROL A. Ranjan, K. Bazargan and M. Sarrafzadeh
- Placement and Routing in 3D Integrated Circuits Cristinel Ababei, Yan Feng, Brent Goplen, Hushrav Mogal,
- 86 Int. J. Embedded Systems, Vol. 2, Nos. 1/2, 2006 Copyright 2006 Inderscience Enterprises Ltd.
- IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, Vol. 24, No. 3, Mar. 2005 1 Abstract--In traditional FPGA placement methods, there is
- IEEE DESIGN & TEST OF COMPUTERS, VOL. XX, NO. Y, FEB. 2000 100 Fast Template Placement for Recon gurable
- Estimation and Optimization of Reliability of Noisy Digital Circuits
- Clustering Based Pruning for Statistical Criticality Computation under Process Variations
- Variation-Aware Routing for FPGAs Satish Sivaswamy
- Microarchitecture Floorplanning for Sub-threshold Leakage Reduction Hushrav D. Mogal and Kia Bazargan
- DEFECT-TOLERANT FPGA ARCHITECTURE EXPLORATION Pongstorn Maidee and Kia Bazargan
- Non-Contiguous Linear Placement for Reconfigurable Fabrics Cristinel Ababei Kia Bazargan
- Incremental Placement for Timing Optimization Wonjoon Choi Kia Bazargan
- Linear Placement for Static / Dynamic Reconfiguration in JBits Vamsi Krishna Marreddy Sharareh Noorbaloochi Kia Bazargan
- Hierarchical Global Floorplacement Using Simulated Annealing and Network Flow Area Migration
- A C to Hardware/Software Compiler Kiarash Bazargan Ryan Kastner Seda Ogrenci Majid Sarrafzadeh
- NOSTRADAMUS: A FLOORPLANNER OF UNCERTAIN DESIGNS K. Bazargan S. Kim M. Sarrafzadeh
- Exploring Potential Benefits of 3D FPGA Integration A new timing-driven partitioning-based placement tool for 3D
- Statistical Timing Driven Partitioning for VLSI Circuits Abstract In this paper we present statistical-timing
- A GENERALIZED AND UNIFIED SPFD-BASED REWIRING TECHNIQUE Pongstorn Maidee and Kia Bazargan
- A Fast SPFD-based Rewiring Technique Pongstorn Maidee
- Fast and Accurate Statistical Criticality Computation under Process Variations
- Enhancing the Memory Performance of Embedded Systems with the FSRAM -1 -Supported in part by the Minnesota Supercomputing Institute.
- Statistical Analysis and Design of HARP Routing Pattern FPGAs
