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Onder, Soner - Department of Computer Science, Michigan Technological University
Improving Software Pipelining by Hiding Memory Latency with Combined Loads and Prefetches
Cost Effective Memory Dependence Prediction using Speculation Levels and Color Sets
Instruction Based Memory Distance Analysis and its Application to Optimization Changpeng Fang
t1=(c==EOF) jmpf t1, L1 t2=(c==EOLN)L1 jmpf t2, L2
Load/Store PC Store Set ID Table
SINAN: An Argument Forwarding Multithreaded Architecture Soner Onder and Rajiv Gupta
Path-based Reuse Distance Analysis Changpeng Fang1, Steve Carr2, Soner Onder2 and Zhenlin Wang2
Unrestricted Code Motion: A Program Representation and Transformation
Load/Store PC Store Set ID Table
Reuse-distance-based Miss-rate Prediction on a Per Instruction Basis
Improving Single-thread Performance with Fine-grain State Maintenance
A Case for a Working-set-based Memory Hierarchy Department of Computer Science
Fast Branch Misprediction Recovery in Out-of-order Superscalar Processors
SPECIFICATION OF INTEL IA-32 USING AN ARCHITECTURE DESCRIPTION LANGUAGE
Instruction Wake-Up in Wide Issue Superscalars Soner Onder Rajiv Gupta
Improving Software Pipelining by Hiding Memory Latency with Combined Loads and Prefetches
Load and Store Reuse Using Register File Contents
Feedback-directed Memory Disambiguation Through Store Distance Analysis
Minor Cycle (Prologue) (Intermission 1)
Copyright 1998 IEEE. Published in the Proceedings of PACT'98, 12-18 October 1998 in Paris, France. Per-
Automatic Generation of Microarchitecture Simulators Soner Onder Rajiv Gupta
