Nourani, Mehrdad - Department of Electrical Engineering, University of Texas at Dallas

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Nourani, Mehrdad - Department of Electrical Engineering, University of Texas at Dallas

Test Access Mechanism for Core Based SystemonChip The Univ. of Texas at Dallas
BuiltInChip Testing of Voltage Overshoots in HighSpeed SoCs Amir Attarha and Mehrdad Nourani
An ILP Formulation to Optimize Test Access Mechanism in SystemonChip Testing
Structural BIST Insertion Using Behavioral Test Analysis y
Efficiency of Adiabatic Logic for Low-Power, Low-Noise VLSI Hamid Mahmoodi-Meimand and Ali Afzali-Kusha
The Effect of Gate Orientation on Fault Detection Mehrdad Nourani and Amir Attarha
A Neural Network Based Algorithm for the Scheduling Problem in HighLevel Synthesis y
Integrated Test of Interacting Controllers and Mehrdad Nourani
An Effective Power Management Scheme for RTL Design Based on Multiple Clocks y
SynthesisforTestability of ControllerDatapath Pairs That Use Gated Clocks
A Layout Estimation Algorithm for RTL Datapaths y Mehrdad Nourani and Christos Papachristou
Structural Fault Testing of Embedded Cores Using Pipelining
A Scheme for Integrated ControllerDatapath Fault Testing Dept. of Electrical & Computer Engineering
An Approach for Redesigning in Data Path Synthesis y Christos Papachristou, Haidar Harmanani and Mehrdad Nourani
Modeling and Simulation of Real Defects Using Fuzzy Logic
False Path Exclusion in Delay Analysis of RTLBased Datapath--Controller Designs y
A Bypass Scheme for CoreBased System Fault Testing y M. Nourani z and C. Papachristou x
IEEE TRANSACTIONS ON VLSI, VOL. XX, NO. Y, MONTH 1999 1 A Multiple Clocking Scheme for Low Power
Avoiding False Paths Caused by Resource Binding in RTL Delay Analysis
IEEE TRANSACTIONS ON VLSI, VOL. XX, NO. Y, MONTH 1999 1 StabilityBased Algorithms for High Level Synthesis
Microprocessor Based Testing for CoreBased System on Chip C. A. Papachristou F. Martin M. Nourani
Detecting Undetectable Controller Faults Using Power Analysis J. Carletta \Lambda C. A. Papachristou y M. Nourani z
Parallelism in Structural Fault Testing of Embedded Cores y M. Nourani z
Signal Integrity: Fault Modeling and Testing in High-Speed SoCs
Testing High-Speed SoCs Using Low-Speed ATEs Mehrdad Nourani
System Requirements for Super Terabit Routing Mehrdad Nourani
Test Pattern Generation for Signal Integrity Faults on Long Interconnects Amir Attarha
An IP Packet Forwarding Technique Based on Partitioned Lookup Table Mohammad J. Akhbarizadeh and Mehrdad Nourani
Move Frame Scheduling and Mixed SchedulingAllocation for the Automated Synthesis of Digital Systems y
Synthesis of Controllers for Full Testability of Integrated DatapathController Pairs Joan Carletta Mehrdad Nourani Christos Papachristou