- On Shortest Path Routing in Single Stage ShuffleExchange Networks \Lambda
- IWIA'04 Technical Program Sunday January 11, 2004
- Performance Evaluation of Memory Caches in Multiprocessors \Lambda YungChin Chen Alexander V. Veidenbaum
- Decoupled Access DRAM Architecture Alexander V. Veidenbaum
- Dynamically Adaptive Fetch Size Prediction for Data Caches Alex Veidenbaum
- IWIA'03 Technical Program Sunday January 26, 2003
- Power Efficient Instruction Cache for Wideissue Processors \Lambda AnaMaria Badulescu, Alexander Veidenbaum
- An Integrated Hardware/Software Data Prefetching Scheme for SharedMemory Multiprocessors \Lambda
- Power-Ecient Instruction Fecth Architecture for Super-Scalar Processors
- Interconnection Network Organization and Its Impact on Performance and Cost
- Adapting Cache Line Size to Application Behavior \Lambda Alexander V. Veidenbaum , Weiyu Tang, Rajesh Gupta,
- they stressed delivered performance, scalabil ity, and programmability. These tests are still
- Non-Sequential Instruction Cache Prefetching for Multiple--Issue Processors
- The Effect of Limited Network Bandwidth and its Utilization by Latency Hiding Techniques in Largescale Shared Memory Systems
- Improving Branch Prediction Accuracy in Embedded Processors in the Presence of Context Switches
- Energy Aware Register File Implementation through Instruction Predecode
- Reducing Power Consumption for High-Associativity Data Caches in Embedded Dan Nicolaescu Alex Veidenbaum Alex Nicolau
- Profile-based Dynamic Voltage Scheduling using Program Checkpoints Ana Azevedo, Ilya Issenin, Radu Cornea
- Integrated I-cache Way Predictor and Branch Target Bu er to Reduce Energy Consumption
- IWIA WORKSHOP January 11, 2007 -January 12, 2007
- IWIA WORKSHOP January 11, 2004 -January 15, 2004
- Sheraton Kauai Reservation Form Sunday, January 26, 2003 -Wednesday, January 29, 2003
- Receive a US Master of Science degree from one of the best public universities in the USA: the University of California (Irvine), while studying in both the US and Italy.
- Reducing Data Cache Energy Consumption via Cached Load/Store Queue
- Scalability of the Cedar System \Lambda Stephen W. Turner Alexander V. Veidenbaum
- Abstract--Instruction queues consume a significant amount of power in high-performance processors, primarily due to
- Secondlevel Cache Organization for Data Prefetching Sunil Kim Alexander V. Veidenbaum
