- IEEE TRANSACTIONS ON COMPUTER-AIDED DESIGN OF INTEGRATED CIRCUITS AND SYSTEMS, VOL. 20, NO. 11, NOVEMBER 2001 1309 Performance and Power Effectiveness in Embedded
- An Integrated Tool for Analog Test Generation and Fault Simulation Sule Ozev and Alex Orailoglu
- Application-Specific Microprocessors 18 0740-7475/03/$17.00 2003 IEEE Published by the IEEE Computer Society IEEE Design & Test of Computers
- Designers use built-in self-test (BIST) in state-of-the-art chip designs to improve test quality and
- Fault Dictionary Size Reduction through Test Response Superposition Baris Arslan and Alex Orailoglu
- Energy Frugal Tags in Reprogrammable I-Caches for Application-Specific Embedded Processors
- Boosting the Accuracy of Analog Test Coverage Computation through Statistical Tolerance Analysis
- 588 IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS--II: ANALOG AND DIGITAL SIGNAL PROCESSING, VOL. 48, NO. 6, JUNE 2001 System-Level Test Synthesis
- Test Selection Based on High Level Fault Simulation for Mixed-Signal Systems
- Aggressive Test Power Reduction Through Test Stimuli Transformation
- Test Application Time and Volume Compression through Seed Overlapping
- Decompression Hardware Determination for Test Volume and Time Reduction
- Virtual Compression through Test Vector Stitching for Scan Based Designs
- Fast and Energy-Frugal Deterministic Test Through Test Vector Correlation Exploitation
- Scan Power Reduction Through Test Data Transition Frequency Analysis
- Test Power Reduction Through Minimization of Scan Chain Transitions
- Space and Time Compaction Schemes for Embedded Cores Ozgur Sinanoglu and Alex Orailoglu
- Compaction Schemes with Minimum Test Application Time Ozgur Sinanoglu and Alex Orailoglu
- Low-power Branch Target Buffer for Application-Specific Embedded Processors
- Customizable Embedded Processor Architectures Peter Petrov
- Power Efficiency through Application-Specific Instruction Memory Transformations
- Low-power Data Memory Communication for Application-Specific Embedded Processors
- Power Efficient Embedded Processor IP's through Application-Specific Tag Compression in Data Caches
- 1132 IEEE TRANSACTIONS ON COMPUTER-AIDED DESIGN OF INTEGRATED CIRCUITS AND SYSTEMS, VOL. 20, NO. 9, SEPTEMBER 2001 Concurrent Test for Digital Linear Systems
- A Novel Scan Architecture for Power-Efficient, Rapid Test Ozgur Sinanoglu and Alex Orailoglu
- Data Cache Energy Minimizations Through Programmable Tag Size Matching to the Applications
- Improving test quality for systems on chips (SOCs) requires fully applying the test
- Test Synthesis for Mixed-Signal SOC Paths Sule Ozev, Ismet Bayraktaroglu, and Alex Orailoglu
- Reducing Test Application Time Through Test Data Mutation Encoding Sherief Reda and Alex Orailoglu
- Partial Core Encryption for Performance-Efficient Test of SOCs
- Speeding Up Control-Dominated Applications through Microarchitectural Customizations in Embedded Processors
- Gate Level Fault Diagnosis in Scan-Based BIST Ismet Bayraktaroglu
- WIRELESS COMMUNICATIONS are becoming the norm for information transmission. Stringent
- 446 IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS, VOL. 8, NO. 4, AUGUST 2000 CMOS technology. Fig. 6 shows the layout of this FIR processor with
- Towards Effective Embedded Processors in Codesigns: Customizable Partitioned Caches
- Cost-Effective Concurrent Test Hardware Design for Linear Analog Circuits Sule Ozev and Alex Orailoglu
- Parity-Based Output Compaction for Core-Based SOCs Ozgur Sinanoglu and Alex Orailoglu
- Compacting Test Responses 2 0740-7475/03/$17.00 2003 IEEE Copublished by the IEEE CS and the IEEE CASS IEEE Design & Test of Computers
- Modeling Scan Chain Modifications For Scan-in Test Power Minimization
