Papaefthymiou, Marios - Department of Electrical Engineering and Computer Science, University of Michigan

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Papaefthymiou, Marios - Department of Electrical Engineering and Computer Science, University of Michigan

An Analysis of Gang Scheduling for Multiprogrammed Parallel Computing Environments
Performance Evaluation of Gang Scheduling for Parallel and Distributed Multiprogramming
Optimizing TwoPhase, LevelClocked Circuitry Alexander T. Ishii
Reconfigurable Low Energy Multiplier for Multimedia System Design Suhwan Kim and Marios C. Papaefthymiou
Asymptotically Efficient Retiming Under Setup and Hold Constraints Marios C. Papaefthymiou
PrecomputationBased Sequential Logic Optimization for Low Power
SinglePhase SourceCoupled Adiabatic Logic Suhwan Kim and Marios C. Papaefthymiou
Optimizing Computations for Effective BlockProcessing \Lambda Kumar N. Lalgudi
LowEnergy Adder Design with a SinglePhase SourceCoupled Adiabatic Logic
Stochastic Analysis of Gang Scheduling in Parallel and Distributed Systems
Implementing and Evaluating Adiabatic Arithmetic Units \Lambda Micah C. Knapp Peter J. Kindlmann Marios C. Papaefthymiou
Tim: A Timing Package for TwoPhase, LevelClocked Circuitry Marios C. Papaefthymiou Keith H. Randall
Optimizing TwoPhase, LevelClocked Circuitry
Efficient Retiming under a General Delay Model Kumar N. Lalgudi and Marios C. Papaefthymiou
Pipelined DSP Design with a True Single-Phase Energy-Recovering Logic Style
EdgeTriggering vs. TwoPhase LevelClocking
DelaY: An Efficient Tool for Retiming with Realistic Delay Modeling Kumar N. Lalgudi Marios C. Papaefthymiou
Memory Assignment for Multiprocessor Caches through Grey Coloring
Understanding Retiming Maximum AverageDelay Cycles
PowerComplexity Analysis of Pipelined VLSI FFT Architectures for Low Energy Wireless Communication Applications
FixedPhase Retiming for Low Power Design Kumar N. Lalgudi and Marios C. Papaefthymiou
Minimizing Sensitivity to Delay Variations in HighPerformance Synchronous Circuits
Analytical Macromodeling for HighLevel Power Estimation Giuseppe Bernacchia
Maximizing Performance by Retiming and Clock Skew Scheduling Xun Liu Marios C. Papaefthymiou
Efficient Pipelining of LevelClocked Circuits with MinMax Propagation Delays
Low Power Parallel Multiplier Design for DSP Applications Through Coefficient Optimization