- Accelerating Biomolecular Simulation using a Scalable Network of Reconfigurable Hardware Arun Patel1
- A Framework for Modeling and Optimization of Prescient Instruction Prefetch
- A Profiler for a Heterogeneous Multi-Core Multi-FPGA System Daniel Pereira Nunes
- To appear at HPCA'96. Please do not distribute. Register File Design Considerations in Dynamically Scheduled Processors
- UTDSP: A VLIW Programmable DSP Sean Hsien-en Peng
- A SYSTEM DESIGN METHODOLOGY FOR REDUCING SYSTEM INTEGRATION TIME AND FACILITATING MODULAR DESIGN VERIFICATION
- A Multiprocessor Viterbi Decoder Using Xilinx FPGAs
- A CMOS Image Sensor for DNA Microarrays Samir Parikh, Glenn Gulak, Paul Chow
- HDLLEVEL PARTITIONING OF CIRCUITS Juan Humberto Rico Romo
- ApplicationSpecific InstructionSet Architectures for Embedded DSP Applications
- Evaluation of the OneChip Reconfigurable Processor
- Memory Interfacing for the OneChip
- Code Compaction for VLIW Instructions Kai-Ting Amy Wang
- Reconfigurable Molecular Dynamics Simulator Navid Azizi, Ian Kuon, Aaron Egier,
- FPGA ACCELERATION OF MONTE-CARLO BASED CREDIT DERIVATIVE PRICING Alexander Kaganov, Paul Chow
- Maximizing System Performance: Using Reconfigurability to Monitor System Communications
- Hardware Support for Prescient Instruction Prefetch Tor M. Aamodt Paul Chow
- MPI as an Abstraction for Software-Hardware Interaction for HPRCs
- Published in Proceedings of the 5th International Conference on Signal Processing Applications
- Submitted to the International Workshop on Compiler and Architecture Support for EmbeddedComputing Systems ---CASES'98. Other work related to this project can be found at http://www.eecg.toronto.edu/~pc/research/dsp/
- Embedded ISA Support for Enhanced FloatingPoint to FixedPoint ANSI C Compilation
- A Multiprocessor Viterbi Decoder Using Xilinx FPGAs David Yeh, Paul Chow, Gennady Feygin
- A 1.2m CMOS FPGA Using Cascaded Logic Blocks and Segmented Routing
- Impact of Intellectual Property Cores on Field Programmable Gate Array
- Alex Kaganov1 ,Daniel Nunes1
- Exploiting Dual DataMemory Banks in Digital Signal Processors Mazen A. R. Saghir, Paul Chow, and Corinna G. Lee
- userfriendly OneChip processor will be found in the heart of future commercial products the following
- Published in Proceedings of the 6th International Conference on Signal Processing Applications
- Published in Proceedings of the 5th International Conference on Signal Processing Applications
- A FieldProgrammable MixedAnalogDigital Array
- Funding for this research has been provided by the Natural Science and Engineering Research Council and the O'Brien Foundation. The prototyping system was provided by CMC/SOCRN. We demonstrated that while using a programmable controller as an
- Numerical Error Minimizing Floating-Point to Fixed-Point ANSI C Compilation
- OneChip: An FPGA Processor With Reconfigurable Logic
- A Scalable FPGA-based Multiprocessor Arun Patel1
- This paper describes the architecture and implementation of a constraintlength 14 Viterbi Decoder that
- A Datapath Compiler with Technology Portability Jianghong Hu
- AN FPGA IMPLEMENTATION OF RECIPROCAL SUMS FOR SPME and Paul Chow
- To appear at HPCA'96. Please do not distribute. Register File Design Considerations in Dynamically Scheduled Processors
- Memory-System Design Considerations for Dynamically-Scheduled Processors Keith I. Farkas
- IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS, VOL. 15, NO. 4, APRIL 2007 377 SIMPPL: An Adaptable SoC Framework Using
- The New Technology Challenge: CMC's Changing Roles
- A Case Study in Design for Reuse Using VHDL Scott Nunweiler
- The Effect of Reconfigurable Units in Superscalar Processors
- Simplifying the Integration of Processing Elements in Computing Systems using a Programmable Controller
- Leveraging Reconfigurability in the Design Process Lesley Shannon and Paul Chow
- DES Cracking on the Transmogrifier 2a Ivan Hamer and Paul Chow
- Compile-Time and Instruction-Set Methods for Improving Floating-to Fixed-Point
- 948 IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS, VOL. 15, NO. 8, AUGUST 2007 QUANTITY PER CLUSTER AND NUMBER OF INPUTS FOR EACH TYPE OF
- IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS, VOL. 7, NO. 2, JUNE 1999 191 The Design of an SRAM-Based Field-Programmable
- FPGA Acceleration of Monte-Carlo Based Credit
- Design of a Versatile and Cost-Effective Hybrid Floating-Point/LNS Arithmetic Processor
- TMD-MPI: AN MPI IMPLEMENTATION FOR MULTIPLE PROCESSORS ACROSS MULTIPLE FPGAS
- Using Reconfigurability to Achieve Real-Time Profiling for Hardware/Software Codesign
- A novel field-programmable mixed-analog-digital array (FPMA) is proposed, which contains a field-programmable
- A 1.2 m CMOS FPGA Using Cascaded Logic Blocks and Segmented Routing
- Design Flow Hardware Infrastructure
- The Routability of Multiprocessor Network Topologies in FPGAs Manuel Saldaa, Lesley Shannon and Paul Chow
- Leveraging Reconfigurability in the Design Process System-on-Chip Design
- Comparison of MD Simulator and Supercomputers
- The LINPACK Benchmark on a Multi-Core Multi-FPGA System Emanuel Caldeira Ramalho
- Hardware Acceleration of Monte-Carlo Structural Financial Instrument Pricing Using a Gaussian Copula Model
- Impact of Intellectual Property Cores on Field Programmable Gate Array
- An Automated Flow to Generate Hardware Computing Nodes from C for an FPGA-Based
- An FPGA Implementation of the Ewald Direct Space and Lennard-Jones
- The Multicluster Architecture: Reducing Cycle Time Through Partitioning Keith I. Farkas
- This paper describes the Transmogrifier2, a second generation multiFPGA system. The largest version of the system will
- MEMORYSYSTEM DESIGN CONSIDERATIONS FOR DYNAMICALLYSCHEDULED MICROPROCESSORS
- IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS, VOL. 7, NO. 3, SEPTEMBER 1999 321 The Design of a SRAM-Based Field-Programmable
- UTDSP: A VLIW DSP Processor in TSMC 0.35 CMOS
- 1. ABSTRACT As custom computing machines evolve, it is clear that
- MemorySystem Design Considerations for DynamicallyScheduled Processors Keith I. Farkas y
- Floating-Point to Fixed-Point Compilation and Embedded Architectural Support
- 1. ABSTRACT As custom computing machines evolve, it is clear that
- MIPS-X INSTRUCTION SET PROGRAMMER'S MANUAL
- The Multicluster Architecture: Reducing Cycle Time Through Partitioning \Lambda Keith I. Farkas y
- A Datapath Compiler with Technology Portability Jianghong Hu
- The Routability of Multiprocessor Network Topologies in Manuel Salda~na, Lesley Shannon and Paul Chow
- A High-speed Inter-process Communication Architecture for FPGA-based Hardware Acceleration of Molecular
- An FPGA Implementation of the Smooth Particle Mesh Ewald
- The Transmogrifier: The University of Toronto FieldProgrammable System
- Published in Proceedings of the 6th International Conference on Signal Processing Applications
- A HighSpeed FPGA Using Programmable Minitiles
- UTDSP: A VLIW Programmable DSP Sean Hsien-en Peng
- A CMOS Imager for DNA Detection Samir Parikh
- Using Reconfigurability to Achieve Real-Time Profiling for Hardware/Software Codesign
- 188 IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS, VOL. 6, NO. 2, JUNE 1998 The Transmogrifier-2: A 1 Million
