
- This paper introduces a methodology for estimation of energy consumption in peripherals such as audio and video devices.
- Task Scheduling for Control Oriented Requirements for Cyber-Physical Systems Fumin Zhang, Klementyna Szwaykowska, Wayne Wolf, and Vincent Mooney
- Combining Data Remapping and Voltage/Frequency Scaling of Second
- April, 2001 CODES 2001 1,2Hardware/Software RTOS Group
- A SystemA System--onon--aa--Chip LockChip Lock Cache with Task PreemptionCache with Task Preemption
- Hardware Support for Real-Time Embedded Multiprocessor System-on-a-Chip Memory Management
- A Comparison of Five Different Multiprocessor SoC Bus Architectures
- Optimizing Energy to Minimize Errors in Dataflow Graphs Using Approximate Adders
- Error-Rate Prediction for Probabilistic Circuits with More General Structures
- Georgia Institute of Technology, 2003 DX-Gt: Memory Management and
- System-on-a-Chip Processor Synchronization Support in Hardware
- PARLAK: Parametrized Lock Cache Generator Bilge E. S. Akgul and Vincent J. Mooney
- Hardware Support for Priority Inheritance
- CREST LCTES/SCOPES 16 July 2002 Georgia Institute of Technology http://www.crest.gatech.edu
- STREAM-ENABLED FILE I/O FOR EMBEDDED SYSTEMS Pramote Kuacharoen
- Combining Data Remapping and Voltage/Frequency Scaling of Second Level Memory for Energy Reduction in Embedded Systems
- Assembly Instruction Level Reverse Execution for Debugging
- HardwareSoftware RunTime Systems and Robotics: A Case Study Vincent John Mooney III 1 , Diego Ruspini 2 , Oussama Khatib 2 and Giovanni De Micheli 1
- System Level Power-Performance Trade-Offs in Embedded Systems Using Voltage and Frequency Scaling of Off-Chip
- Timing Analysis for Preemptive Multi-tasking Real-Time Systems with Caches Yudong Tan and Vincent J. Mooney III, {ydtan, mooney}@ece.gatech.edu
- October 2002 ISSS 1Center for Research on Embedded Systems and Technology
- 2004 Georgia Institute of Technology Automated Bus Generation
- Round-robin Arbiter Design and Eung S. Shin
- The Emerging Power Crisis in Embedded Processors: What can a (poor) Compiler do?
- Synthesis From Mixed Specifications Vincent J. Mooney III
- ASP-DAC 2004 1 Golay and Wavelet Error
- I-Slate, Ethnomathematics and Rural Education Krishna Palem#1
- Dynamic Memory Management for Real-Time Multiprocessor
- Integrated Intra-and Inter-Task Cache Analysis for Preemptive Multi-tasking Real-Time Systems
- Path-Based Edge Activation for Dynamic Run-Time Scheduling
- Kyeong Keol Ryu and Vincent J. Mooney III School of Electrical and Computer Engineering
- Vincent J. Mooney III, 2006Vincent J. Mooney III, 2006 Sleepy Keeper : a New
- RunTime Scheduler Synthesis For HardwareSoftware Systems and
- Design Space Optimization of Embedded Memory Systems via Data Remapping
- Vincent J. Mooney III, 2007FPGAworldFPGAworld 13 September 200713 September 2007 Research Trends in Hardware/
- Cache-related Timing Analysis for Preemptive Multi-tasking Real-Time
- Sleepy stack: a New Approach to Low Power VLSI Logic and Memory
- DX-Gt: Memory Management and Crossbar Switch Generator for Multiprocessor System-on-a-Chip
- Golay and Wavelet Error Control Codes in VLSI Abstract This paper presents a high speed VLSI
- Embedded Software StreamingEmbedded Software Streaming via Block Streamvia Block Stream
- WCRT Analysis for a Uniprocessor with a Unified Prioritized Center for Research on Embedded Systems and Technology
- 20042004--1111--88 SCOPESSCOPES''04, September 200404, September 2004 11 Integrated IntraIntegrated Intra--and Interand Inter--tasktask
- FPGA World 2004FPGA World 2004 HW/SW RTOS Project of the HW/SW Codesign Group at GTHW/SW RTOS Project of the HW/SW Codesign Group at GT Vincent J. Mooney III, 2004
- 20052005--55--1212 2005 Georgia Institute of Technology2005 Georgia Institute of Technology Cache Design and TimingCache Design and Timing
- PhD Dissertation DefensePhD Dissertation Defense Bilge E. S. Akgul
- Automated Generation of Round-robin
- !#"%$'&)(1023 4 0&6587@9A"CB DFEGHPIRQTSVU4W'XAQTQTS`Y
- Pareto Points in SRAM Design Using the Sleepy Stack Approach Jun Cheol Park and Vincent J. Mooney III
- Georgia Institute of Technology, 2005Georgia Institute of Technology, 2005 Pareto Points in SRAM Design
- Sleepy Stack Reduction of Leakage Power Jun Cheol Park, Vincent J. Mooney III, and Philipp Pfeiffenberger
- Interconnect Delay Aware RTL Verilog Bus Architecture Generation for an SoC Kyeong Keol Ryu*, Alexandru Talpasanu, Vincent J. Mooney III* and Jeffrey A. Davis
- Interconnect Delay Aware RTL Verilog Bus Architecture
- Energy Estimation of Peripheral Devices in Embedded Systems Vincent J. Mooney III
- Golay and Wavelet Error Control Codes in VLSI Arunkumar Balasundaram*,&, Angelo Pereira&, Jun Cheol Park*,& and Vincent J. Mooney III*,&,+
- A Prioritized Cache for Multi-tasking Real-Time Systems Abstract: In this paper, we present a new prioritized cache
- A Prioritized Cache for Multi-tasking Real-time Systems
- Automated Bus Generation for Multiprocessor SoC Design Kyeong Keol Ryu and Vincent J. Mooney III
- Vincent J. Mooney IIIVincent J. Mooney III http://http://codesign.ece.gatech.educodesign.ece.gatech.edu
- Custom hardware: SoC Lock Cache (SoCLC) SoCLC provides lock-based synchronization
- Energy Minimization of a Pipelined Processor using a Low Voltage Pipelined Cache
- Energy Minimization of Pipeline Processor Using a Low Voltage
- Instruction-level Reverse Execution for Debugging Tankut Akgul and Vincent J. Mooney III
- Round-robin Arbiter Design and Generation Eung S. Shin, Vincent J. Mooney III and George F. Riley
- The Emerging Power Crisis in EmbeddedThe Emerging Power Crisis in Embedded Processors What Can a (Poor) Compiler Do ?Processors What Can a (Poor) Compiler Do ?
- A System-on-a-Chip Lock Cache with Task Preemption Support
- Georgia Tech, 2001. Confidential & Proprietary Adaptability, Extensibility, and Flexibility in
- A Comparison of Five Different Multiprocessor SoC Bus Architectures
- System-on-a-Chip Processor Synchronization
- A Dynamic Memory Management Unit for Embedded Real-Time System-on-a-Chip
- Instruction-level Reverse Execution for Debugging Tankut Akgul and Vincent J. Mooney III
- Sleepy Keeper: a New Approach to Low-leakage Power VLSI Design
- Instruction-level Reverse Execution for Debugging
- Sleepy Stack Reduction of Leakage Power
- A More Precise Model of Noise Based CMOS Errors Arun Bhanu, Mark S. K. Lau, Keck-Voon Ling, Vincent J. Mooney III, Anshul Singh
- Traditional Loss-Tolerant and Secure Embedded Computing
- Low Power Motion Estimation with Probabilistic Charvi Dhoot