Diessel, Oliver - School of Computer Science and Engineering, University of New South Wales

• MODULE GRAPH MERGING AND PLACEMENT TO REDUCE RECONFIGURATION OVERHEADS IN PAGED FPGA DEVICES
• MES Workshop Singapore 2007
• Generating the Communications Infrastructure for Module-based Dynamic
• Configuration Encoding Techniques for Fast FPGA Reconfiguration
• Institut fr Angewandte Informatik und Formale Beschreibungsverfahren
• NoC support for dynamic FPGA pages Eduard Warkentin
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• FPGA-Based Video Processing for a Vision Prosthesis
• ICAP-I: A Reusable Interface for the Internal Reconfiguration of Xilinx FPGAs
• ACS: an Addressless Configuration Support for Efficient Partial Reconfigurations
• Communications Infrastructure Generation for Modular FPGA Reconfiguration
• Functional Unit Chaining: A Runtime Adaptive Architecture for Reducing Bypass Delays
• THE ENTROPY OF FPGA RECONFIGURATION Usama Malik and Oliver Diessel
• A Configuration System Architecture Supporting Bit-stream Compression for FPGAs
• Population based Ant Colony Optimization on FPGA , M. Middendorf
• Resource-Aware Run-time Elaboration of Behavioural FPGA Specifications U. Malik, K. So, O. Diessel
• Towards High-Level Specification, Synthesis, and Virtualization of Programmable Logic Designs
• An FPGA Interpreter with Virtual Hardware Management Oliver Diessel Usama Malik
• On Scheduling Dynamic FPGA Recon gurations Oliver Diessel1 and Hossam ElGindy2
• Partial Rearrangements of Space{shared FPGAs (Extended Abstract)
• Partial Task Compaction Reduces Queuing Delays in Partitionable{Array Machines
• Proceedings 2004 IEEE International Conference on
• Towards Dilated Placement of Dynamic NoC Cores
• Reconfigurable Computing 29 November 2006 Reconfigurable Computing
• Page 1 of 17 COMMA: A Communications Methodology for
• A Configuration Memory Architecture for Fast FPGA Reconfiguration
• Opportunities for Operating Systems Research in Recon gurable Computing
• On Scheduling Dynamic FPGA Recon gurations
• Partial FPGA Rearrangement by Local Repacking Oliver Diessel1 and Hossam ElGindy2
• Ordered Partial Task Compaction on Mesh Connected Computers
• UNSW Co-op Program ITE Guidelines 2011 CO-OP PROGRAM
• Co-op Scholar IT Check List CO-OP PROGRAM IT CHECKLIST FOR SUPERVISORS
• Applied Soft Computing 4 (2004) 303322 FPGA implementation of population-based ant
• A Web{Based Multiuser Operating System for Recon gurable Computing
• Fast Code-Phase Alignment of GPS
• National ICT Australia Reconfigurable Computing Workshop
• COMMA: A Communications Methodology for Dynamic Module Reconfiguration in FPGAs (Extended Abstract)
• Software Engineering Co-op Program January 16, 2009
• Towards High-Level Specification & Synthesis of Dynamic Process Logic
• Enabling RTR for Industry Oliver Diessel & Shannon Koh
• Partial FPGA Rearrangement by Local Repacking Oliver Diessel1 and Hossam ElGindy2
• Dynamic Scheduling of Tasks on Partially Recon gurable Oliver Diessel
• Run{Time Compaction of FPGA Designs Oliver Diessel1 and Hossam ElGindy2
• Operating Systems Support for Dynamically Reconfigurable Architectures
• A CONFIGURATION MEMORY ARCHITECTURE FOR FAST RUN-TIME RECONFIGURATION OF FPGAS
• COMMA: A Communications Methodology for Dynamic Module-based Reconfiguration of FPGAs
• The Effectiveness of Configuration Merging in Point-to-Point Networks for Module-based FPGA Reconfiguration
• Proceedings of the 2009 International Conference on
• E cient Broadcasting Procedures for Constrained Recon gurable Meshes
• Optimal Algorithms for Constrained Recon gurable Meshes B. Beresford{Smith O. Diessel H. ElGindy
• Optimal Algorithms for Constrained Recon gurable Meshes
• Configuration Merging in Point-to-Point Networks for Module-based FPGA Reconfiguration
• On the Placement and Granularity of FPGA Configurations Usama Malik
• 2010 CMP Co-Op Program COMP1917 Higher Computing 1 6 -
• Modeling Dynamically Reconfigurable Systems for Simulation-based Functional Verification
• ReSim: A Reusable Library for RTL Simulation of Dynamic Partial Reconfiguration
• Optimization of Placement of Dynamic Network-on-chip Cores Using Simulated Annealing