- To appear at The 34th Annual International Symposium on Microarchitecture, December 2001.
- To appear in ASPLOS-V Conference Proceedings, October 1992 1 Sentinel Scheduling for VLIW and Superscalar Processors
- APPENDIX A. PERFORMANCE RESULTS FOR ALL PROCESSOR CONFIGURATIONS
- Proceedings of the 20th Annual International Conference on Parallel Processing, pp. 142-145. 142 THE EFFECT OF COMPILER OPTIMIZATIONS ON AVAILABLE PARALLELISM IN
- Register Connection: A New Approach to Adding Registers into Instruction Set Architectures
- Appears in Proceedings of the 26th Annual Intl. Symposium on Computer Architecture ISCA, pp. 136 147, May 1999. A Hardware-Driven Pro ling Scheme for Identifying Program Hot
- To appear in MICRO-25 Conference Proceedings, December 1992 1 Enhanced Modulo Scheduling for Loops with Conditional Branches
- Speculative Hedge: Regulating Compile-Time Speculation Against Pro le Variations
- CODE SCHEDULING AND OPTIMIZATION FOR A SUPERSCALAR X86 MICROPROCESSOR
- To appear in MICRO25 Conference Proceedings, December 1992 1 Enhanced Modulo Scheduling for Loops with Conditional Branches
- To appear: Proceedings of Supercomputing '92 1 Compiler Code Transformations for SuperscalarBased
- Characterizing the Impact of Predicated Execution on Branch Prediction
- Speculative Execution Exception Recovery Write-back Suppression
- Characterizing the Impact of Predicated Execution on Branch Prediction
- A Study of the Cache and Branch Performance Issues with Running Java on Current Hardware Platforms
- Copyright by John Christopher Gyllenhaal, 1997 AN EFFICIENT FRAMEWORK FOR PERFORMING
- Proceedings of the 20th Annual International Conference on Parallel Processing, pp. 142145. 142 THE EFFECT OF COMPILER OPTIMIZATIONS ON AVAILABLE PARALLELISM IN
- Proceedings of the 18th International Symposium on Computer Architecture, pp. 266-275, 1991 266 IMPACT: An Architectural Framework for
- A Framework for Balancing Control Flow and Predication David I. August Wen-mei W. Hwu Scott A. Mahlke
- Published in HICSS-26 Conference Proceedings, January 1993, Vol. 1, pp. 497-506. 1 The Bene t of Predicated Execution for Software Pipelining
- c Copyright by Matthew Carl Merten, 1999 A FRAMEWORK FOR PROFILE-DRIVEN OPTIMIZATION
- Proceedings of the 33rd Annual ACM/IEEE International Symposium on Microarchitecture, pp. 112--123, December 2000. Copyright c
- fl Copyright by Christopher Neith George, 1999 A FRAMEWORK FOR INSTALLTIME OPTIMIZATION
- Three Architectural Models for CompilerControlled Speculative Execution
- Code Scheduling for VLIW Superscalar Processors with Limited Register Files
- Pro le-Assisted Instruction Scheduling William Y. Chen Scott A. Mahlke Nancy J. Warter Sadun Anik Wen-mei W. Hwu
- APPENDIX A. PERFORMANCE RESULTS FOR ALL PROCESSOR CONFIGURATIONS
- Appeared in ASPLOS-VI Proceedings, Oct 1994 1 Dynamic Memory Disambiguation Using the Memory Con ict Bu er
- Runtime Cache Hierarchy Management via Reference Analysis Teresa L. Johnson \Lambda Wenmei W. Hwu
- fl Copyright by Richard Eugene Hank, 1996 REGIONBASED COMPILATION
- SOFTWARE---PRACTICE AND EXPERIENCE, VOL. 24(9), 1--20(September 1994) Incremental Compiler Transformations For Multiple
- DESIGN AND IMPLEMENTATION OF A PORTABLE GLOBAL CODE OPTIMIZER
- AN OVERVIEW OF THE IMPACT x86 BINARY REOPTIMIZATION FRAMEWORK
- MACHINE INDEPENDENT REGISTER ALLOCATION FOR THE IMPACTI C COMPILER
- Runtime Spatial Locality Detection and Optimization Teresa L. Johnson Matthew C. Merten Wenmei W. Hwu
- Integrated Predicated and Speculative Execution in the IMPACT EPIC Architecture
- fl Copyright by Matthew Carl Merten, 1999 A FRAMEWORK FOR PROFILEDRIVEN OPTIMIZATION
- SUPPORTING PREDICATED EXECUTION: TECHNIQUES AND TRADEOFFS JAMES EARL MCCORMICK, JR.
- RegionBased Compilation: An Introduction and Motivation Richard E. Hank Wenmei W. Hwu
- HardwareDriven Identifying
- UnrollingBased Optimizations for Modulo Scheduling Daniel M. Lavery Wenmei W. Hwu
- To appear -ISCA-22, Jun 1995 1 A Comparison of Full and Partial Predicated Execution Support
- OPTIMIZATION AND EXECUTABLE REGENERATION IN THE IMPACT BINARY REOPTIMIZATION FRAMEWORK
- Proceedings of the 24th International Symposium on Microarchitecture MICRO24 1 Data Access Microarchitectures for Superscalar Processors
- HMDES Version 2.0 Speci cation John C. Gyllenhaal Wen-mei W. Hwu
- A Framework for Balancing Control Flow and Predication David I. August Wenmei W. Hwu Scott A. Mahlke
- Proceedings of the 18th International Symposium on Computer Architecture, pp. 266275, 1991 266 IMPACT: An Architectural Framework for
- Appeared in ASPLOSVI Proceedings, Oct 1994 1 Dynamic Memory Disambiguation Using the Memory Conflict Buffer
- The E ect of Code Expanding Optimizations on Instruction Cache Design
- Java Bytecode to Native Code Translation: The Caffeine Prototype and Preliminary Results
- Comparing Software and Hardware Schemes For Reducing the Cost of Branches
- Technical Report IMPACT9702 1 Runtime Spatial Locality Detection and Optimization \Lambda
- Modulo Schedule Buffers Matthew C. Merten and Wenmei W. Hwu
- A SoftwareOriented FloatingPoint Format for Enhancing Automotive Control Systems
- CompilerAssisted Multiple Instruction Retry ChungChi Jim Li, ShyhKwei Chen, W. Kent Fuchs, and WenMei W. Hwu
- E cient Instruction Sequencing with Inline Target Insertion1 Wen-mei W. Hwu, Member IEEE, 2 and Pohua P. Chang3
- Technical Report IMPACT-97-02 1 Run-time Spatial Locality Detection and Optimization
- Run-time Cache Hierarchy Management via Reference Analysis Teresa L. Johnson Wen-mei W. Hwu
- Reducing Cache Misses in Numerical Applications Using Data Relocation and Prefetching
- c Copyright by YOJI YAMADA, 1995 DATA RELOCATION AND PREFETCHING FOR PROGRAMS WITH LARGE DATA SETS
- Proceedings of the 24th International Symposium on Microarchitecture -MICRO24 1 Data Access Microarchitectures for Superscalar Processors
- A MULTIPORTED NONBLOCKING CACHE FOR A SUPERSCALAR UNIPROCESSOR
- c Copyright by William Yu-Wei Chen, Jr., 1993 DATA PRELOAD FOR SUPERSCALAR AND VLIW PROCESSORS
- SUPPORTING PREDICATED EXECUTION: TECHNIQUES AND TRADEOFFS JAMES EARL MCCORMICK, JR.
- The Importance of Prepass Code Scheduling for Superscalar and Superpipelined Processors
- c Copyright by Nancy Jeanne Warter, 1994 MODULO SCHEDULING WITH ISOMORPHIC CONTROL TRANSFORMATIONS
- Proceedings of the 24th International Symposium on Microarchitectures -MICRO24 1 Comparing Static And Dynamic Code Scheduling
- EVALUATION OF SOME SUPERSCALAR AND VLIW PROCESSOR DESIGNS JOHN GUSTAF HOLM
- c Copyright by Thomas Martin Conte, 1992 SYSTEMATIC COMPUTER ARCHITECTURE PROTOTYPING
- Performance Implications of Synchronization Support for Parallel Fortran Programs
- c Copyright by Dimitri Carl Argyres, 1995 PERFORMANCE AND COST ANALYSIS
- COMPILER SUPPORT FOR SPARC ARCHITECTURE PROCESSORS ROLAND G. OUELLETTE
- 1. INTRODUCTION......................................................................................................1 1.1 The AMD K5 Microprocessor......................................................................2
- Proceedings of the 21st Annual International Conference on Parallel Processing 1 TOLERATING FIRST LEVEL MEMORY ACCESS LATENCY
- ARCHITECTURAL AND SOFTWARE SUPPORT FOR EXECUTING NUMERICAL APPLICATIONS ON HIGH PERFORMANCE COMPUTERS
- Copyright by John Christopher Gyllenhaal, 1997 AN EFFICIENT FRAMEWORK FOR PERFORMING
- Pro le-Guided Automatic Inline Expansion for C Programs Pohua P. Chang, Scott A. Mahlke, William Y. Chen and Wen-mei W. Hwu
- Control Flow Optimization for Supercomputer Scalar Processing Pohua P. Chang and Wen-mei W. Hwu
- Region-Based Compilation: An Introduction and Motivation Richard E. Hank Wen-mei W. Hwu
- Superblock Formation Using Static Program Analysis Richard E. Hank Scott A. Mahlke Roger A. Bringmann John C. Gyllenhaal Wen-mei W. Hwu
- The Superblock: An E ective Technique for VLIW and Superscalar Compilation
- Compiler-Assisted Multiple Instruction Retry Chung-Chi Jim Li, Shyh-Kwei Chen, W. Kent Fuchs, and Wen-Mei W. Hwu
- Code Reordering and Speculation Support for Dynamic Optimization Systems Erik M. Nystrom, Ronald D. Barnes, Matthew C. Merten, Wen-mei W. Hwu
- c Copyright by Roger Alexander Bringmann, 1995 ENHANCING INSTRUCTION LEVEL PARALLELISM
- Sentinel Scheduling with Recovery Blocks David I. August Brian L. Deitrich Scott A. Mahlke
- An Architectural Framework for Run-Time Optimization
- c Copyright by Christopher Neith George, 1999 A FRAMEWORK FOR INSTALL-TIME OPTIMIZATION
- OPTIMIZATION AND EXECUTABLE REGENERATION IN THE IMPACT BINARY REOPTIMIZATION FRAMEWORK
- An Execution Pro ler for Window-oriented Applications Aloke Gupta and Wen-Mei W. Hwu
- PERFORMANCE ASPECTS OF COMPUTERS WITH GRAPHICAL USER INTERFACES
- A Software-Oriented Floating-Point Format for Enhancing Automotive Control Systems
- ProfileAssisted Instruction Scheduling William Y. Chen Scott A. Mahlke Nancy J. Warter Sadun Anik Wenmei W. Hwu
- Hardware Support for Dynamic Activation of CompilerDirected Computation Reuse
- Run-time Cache Bypassing Teresa L. Johnson y Daniel A. Connors z Matthew C. Merten z Wen-mei W. Hwu z
- A TEMPLATE FOR CODE GENERATOR DEVELOPMENT USING THE IMPACTI C COMPILER
- Appears in Proceedings of the 26th Annual Intl. Symposium on Computer Architecture (ISCA), pp. 136--147, May 1999. A HardwareDriven Profiling Scheme for Identifying Program Hot
- Compiler Technology for Future Microprocessors Wen-mei W. Hwu Richard E. Hank David M. Gallagher Scott A. Mahlkey
- Comparing Software and Hardware Schemes For Reducing the Cost of Branches
- UrbanaChampaign www.crhc.uiuc.edu/IMPACT
- # Copyright by Daniel Alexander Connors, 2000 ELIMINATING DYNAMIC COMPUTATION REDUNDANCY
- A MACHINE DESCRIPTION LANGUAGE FOR COMPILATION
- Modulo Schedule Buffers Matthew C. Merten and Wen-mei W. Hwu
- Reducing Cache Misses in Numerical Applications Using Data Relocation and Prefetching
- Optimization of Machine Descriptions for Efficient Use John C. Gyllenhaal Wenmei W. Hwu
- 1. INTRODUCTION ......................................................................................................1 1.1 The AMD K5 Microprocessor ......................................................................2
- Superblock Formation Using Static Program Analysis Richard E. Hank Scott A. Mahlke Roger A. Bringmann John C. Gyllenhaal Wenmei W. Hwu
- Using NET to Capture Performance in JavaBased Software ChengHsueh A. Hsieh Marie T. Conte Teresa L. Johnson John C. Gyllenhaal
- Speculative Hedge: Regulating CompileTime Speculation Against Profile Variations
- Compiler Technology for Future Microprocessors Wenmei W. Hwu Richard E. Hank David M. Gallagher \Lambda Scott A. Mahlke y
- Appears in Proceedings of the 27th Annual Intl. Symposium on Computer Architecture (ISCA), pp. 59--70, June 2000. A Hardware Mechanism for Dynamic Extraction and
- Copyright by Christopher John Shannon, 2002 THE IMPACT SC140 CODE GENERATOR
- Unrolling-Based Optimizations for Modulo Scheduling Daniel M. Lavery Wen-mei W. Hwu
- Characterization of Repeating Data Access Patterns in Integer Benchmarks
- SOFTWARE--PRACTICE AND EXPERIENCE, VOL. 24(9), 120(September1994) Incremental Compiler Transformations For Multiple
- COMPILER SUPPORT FOR PREDICATED EXECUTION IN SUPERSCALAR PROCESSORS
- Proceedings of the 33rd Annual ACM/IEEE International Symposium on Microarchitecture, pp. 112123, December 2000. Copyright c
- Three Superblock Scheduling Models for Superscalar and Superpipelined Processors
- Integrated Predicated and Speculative Execution in the IMPACT EPIC Architecture
- A Study of the Cache and Branch Performance Issues with Running Java on Current Hardware Platforms
- Effective Compiler Support for Predicated Execution Using the Hyperblock
- Proceedings of the 1992 International Conference on Supercomputing. 1 Tolerating Data Access Latency with Register Preloading
- Data Relocation and Prefetching for Programs with Large Data Sets
- Data Relocation and Prefetching for Programs with Large Data Sets
- A Study of Code Reuse and Sharing Characteristics of Java Applications
- Proceedings of the 24th International Symposium on Microarchitectures MICRO24 1 Comparing Static And Dynamic Code Scheduling
- An Architectural Framework for RunTime Optimization
- Proceedings of the 21st Annual International Conference on Parallel Processing 1 TOLERATING FIRST LEVEL MEMORY ACCESS LATENCY
- CompilerDirected Early LoadAddress Generation BenChung Cheng \Lambda Daniel A. Connors y Wenmei W. Hwu y
- MACHINE INDEPENDENT REGISTER ALLOCATION FOR THE IMPACT-I C COMPILER
- Proceedings of the 21st Annual International Conference on Parallel Processing 1 EXECUTING NESTED PARALLEL LOOPS ON SHARED-MEMORY
- Three Architectural Models for Compiler-Controlled Speculative Execution
- Published in HICSS26 Conference Proceedings, January 1993, Vol. 1, pp. 497506. 1 The Benefit of Predicated Execution for Software Pipelining
- A TEMPLATE FOR CODE GENERATOR DEVELOPMENT USING THE IMPACT-I C COMPILER
- To appear: Proceedings of Supercomputing '92 1 Compiler Code Transformations for Superscalar-Based
- Using NET to Capture Performance in Java-Based Software Cheng-Hsueh A. Hsieh Marie T. Conte Teresa L. Johnson John C. Gyllenhaal
- A Study of Code Reuse and Sharing Characteristics of Java Applications
- To appear at The 34th Annual International Symposium on Microarchitecture, December 2001.
- Control Flow Optimization for Supercomputer Scalar Processing Pohua P. Chang and Wenmei W. Hwu
- Proceedings of the 21st Annual International Conference on Parallel Processing 1 EXECUTING NESTED PARALLEL LOOPS ON SHAREDMEMORY
- To appear in ASPLOSV Conference Proceedings, October 1992 1 Sentinel Scheduling for VLIW and Superscalar Processors
- HMDES Version 2.0 Specification John C. Gyllenhaal Wenmei W. Hwu
- E ective Compiler Support for Predicated Execution Using the Hyperblock
- The Program Decision Logic Approach to Predicated Execution David I. August John W. Sias Jean-Michel Puiatti
- ProfileGuided Automatic Inline Expansion for C Programs Pohua P. Chang, Scott A. Mahlke, William Y. Chen and Wenmei W. Hwu
- UrbanaChampaign www.crhc.uiuc.edu/IMPACT
- To Appear in Proceedings of the 32nd Annual International Symposium on Microarchitecture (MICRO), November 1999. CompilerDirected Dynamic Computation Reuse: Rationale and Initial Results
- Code Reordering and Speculation Support for Dynamic Optimization Systems Erik M. Nystrom, Ronald D. Barnes, Matthew C. Merten, Wenmei W. Hwu
- Speculative Execution Exception Recovery Writeback Suppression
- A Hardware-Driven Profiling Scheme for Identifying Program Hot Spots to Support Runtime Optimization
- Run-time Spatial Locality Detection and Optimization Teresa L. Johnson Matthew C. Merten Wen-mei W. Hwu
- Characterization of Repeating Data Access Patterns in Integer Benchmarks
- The Importance of Prepass Code Scheduling for Superscalar and Superpipelined Processors
- Code Scheduling for VLIW/Superscalar Processors with Limited Register Files
- The Program Decision Logic Approach to Predicated Execution David I. August John W. Sias JeanMichel Puiatti \Lambda Scott A. Mahlke y
- Proceedings of the 25th Annual Hawaii International Conference on System Sciences, 1992 1 Scalar Program Performance on MultipleInstructionIssue Processors
- Register Connection: A New Approach to Adding Registers into Instruction Set Architectures
- Performance Implications of Synchronization Support for Parallel Fortran Programs
- AN OPTIMIZING COMPILER CODE GENERATOR: A PLATFORM FOR RISC PERFORMANCE ANALYSIS
- Java Bytecode to Native Code Translation: The Caffeine Prototype and Preliminary Results
- Proceedings of the 25th Annual Hawaii International Conference on System Sciences, 1992 1 Scalar Program Performance on Multiple-Instruction-Issue Processors
- To appear ISCA22, Jun 1995 1 A Comparison of Full and Partial Predicated Execution Support
- The Superblock: An Effective Technique for VLIW and Superscalar Compilation
- Efficient Instruction Sequencing with Inline Target Insertion 1 Wenmei W. Hwu, Member IEEE, 2 and Pohua P. Chang 3
- Optimization of Machine Descriptions for Efficient Use John C. Gyllenhaal Wen-mei W. Hwu
- Appears in Proceedings of the 27th Annual Intl. Symposium on Computer Architecture (ISCA), pp. 5970, June 2000. A Hardware Mechanism for Dynamic Extraction and
- c Copyright by Richard Eugene Hank, 1996 REGION-BASED COMPILATION
- Proceedings of the 1992 International Conference on Supercomputing. 1 Tolerating Data Access Latency with Register Preloading
