- Using Predicate Path Information in Hardware to Determine True Dependences
- Deterministic Memory-Efficient String Matching Algorithms for Intrusion Detection
- In Proceedings of the 37th International Symposium on Microarchitecture, December, 2004 Hardware and Binary Modification Support for Code
- Overlapping Execution with Transfer Using Non-Strict Execution for Mobile Programs
- Published in the 5th International Symposium On High Performance Computer Architecture, January 1999. Instruction Recycling on a Multiple-Path Processor
- Dynamic Code Value Specialization Using the Trace Cache Fill Unit
- Instruction Cache Fetch Policies for Speculative Execution Dennis Lee and Jean-Loup Baer
- Journal of Machine Learning Research 7 (2006) 343378 Submitted 7/05; Revised 12/05; Published 2/06 Using Machine Learning to Guide Architecture Simulation
- In Proceedings of the International Conference on Parallel Architectures and Compilation Techniques (PACT), September 2001.
- Optimizations Enabled by a Decoupled Front-End Architecture Glenn Reinmany
- UNIVERSITY OF CALIFORNIA, SAN DIEGO Application-Tuned Processor Architectures
- Automatically Characterizing Large Scale Program Behavior
- In Proceedings of the 3rd International Symposium on High Performance Computing (ISHPC2K), October 2000, (c) Springer-Verlag.
- Automatic Logging of Operating System Effects to Guide Application-Level Architecture Simulation
- Patchable Instruction ROM Architecture Timothy Sherwood Brad Calder
- IEEE International Parallel and Distributed Processing Symposium, April 2005 A Dependency Chain Clustered Microarchitecture
- Cross Binary Simulation Points Erez Perelman Jeremy Lau Harish Patil Aamer Jaleel
- Using SimPoint for Accurate and Efficient Simulation Erez Perelman Greg Hamerly Michael Van Biesbrouck
- In Proceedings of the International Symposium on Code Generation and Optimization (CGO 2006). A Self-Repairing Prefetcher in an
- Balancing Design Options with Sherpa Timothy Sherwood Mark Oskin
- IEEE International Parallel and Distributed Processing Symposium (IPDPS), April 2006 Detecting Phases in Parallel Applications on
- Published in the Proceedings of the Annual 31st International Symposium on Microarchitecture, December 1998. Predictive Techniques for Aggressive Load Speculation
- A version of this paper appeared in the ACM Transactions on Programming Languages and Systems, 19(1), 1997. Evidence-based Static Branch Prediction using Machine Learning
- In proceedings of the 9th International Symposium on High Performance Computer Architecture, February 2003. Catching Accurate Profiles in Hardware
- In Proceedings of the 13th International Symposium on High Performance Computer Architecture (HPCA 2007). Accelerating and Adapting Precomputation Threads for Efficient Prefetching
- Bounds Checking with Taint-Based Analysis Weihaw Chuang Satish Narayanasamy Brad Calder
- Modern computer architecture research relies heavily on cycle-accurate simu-
- Exploiting Program Microarchitecture Independent Characteristics and Phase Behavior for Reduced
- In Proceedings of the International Conference on Parallel Architectures and Compilation Techniques (PACT), Sept. 2005. Variational Path Profiling
- Journal of Instruction-Level Parallelism 7 (2005) 1-28 Submitted 6/2005; published 9/2005 SimPoint 3.0: Faster and More Flexible
- IEEE International Symposium on Performance Analysis of Systems and Software, March 2005 The Strong Correlation Between Code Signatures and Performance
- In the 11th International Symposium on High Performance Computer Architecture, February 2005 Transition Phase Classification and Prediction
- BitRaker Anvil: Binary Instrumentation for Rapid Creation of Simulation and Workload Analysis Tools
- How to Use SimPoint to Pick Simulation Points Greg Hamerly Erez Perelman Brad Calder
- Using a Serial Cache for Energy Efficient Instruction Fetching
- IEEE International Symposium on Performance Analysis of Systems and Software, March 2004 A Co-Phase Matrix to Guide Simultaneous Multithreading Simulation
- In proceedings of the 10th International Symposium on High Performance Computer Architecture, February 2004. Creating Converged Trace Schedules Using String Matching
- Understanding program behavior is at the foundation of computer architecture
- Reducing Code Size With Echo Instructions Jeremy Lau Stefan Schoenmackers Timothy Sherwood Brad Calder
- In Proceedings of the International Conference on Parallel Architectures and Compilation Techniques (PACT), September 2003.
- In Proceedings of the 30th International Symposium on Computer Architecture (ISCA), June 2003. A Pipelined Memory Architecture for High Throughput Network Processors
- In Proceedings of the 30th International Symposium on Computer Architecture (ISCA), June 2003. Phase Tracking and Prediction
- Predicate Prediction for Efficient Out-of-order Execution Weihaw Chuang Brad Calder
- In Proceedings of the 4th International Symposium on High Performance Computing (ISHPC), May 2002, (c) Springer-Verlag. An EPIC Processor with Pending Functional Units
- In Proceedings of the 28th International Symposium on Computer Architecture (ISCA), June 2001. Automated Design of Finite State Machine Predictors
- Reducing the Overhead of Dynamic Compilation Chandra Krintzy
- In Proceedings of the 33rd Annual International Symposium on Microarchitecture (MICRO-33), December 2000. Predictor-Directed Stream Buffers
- In Proceedings of the 3rd International Symposium on High Performance Computing (ISHPC2K), October 2000, (c) Springer-Verlag.
- Published in the International European Conference on Parallel Computing (EURO-PAR), August 2000. ToolBlocks: An Infrastructure for the Construction
- Reducing Transfer Delay Using Java Class File Splitting and Prefetching Chandra Krintz Brad Calder Urs Holzle
- Reducing Cache Misses Using Hardware and Software Page Placement Timothy Sherwood Brad Calder Joel Emer
- Computing Along the Critical Path Dean M. Tullsen Brad Calder
- Appeared in the 3rd Workshop on Interaction between Compilers and Computer Architectures, October 1998. A Comparison of Software Code Reordering
- Copyright 1997 IEEE. Published in the Proceedings of Micro-30, December 1-3, 1997 in Research Triangle Park, North Carolina. Personal use of this material is permitted. However, permission to reprint/republish this material for advertising or promotional
- Procedure Placement Using Temporal Ordering Information Nikolas Gloy, Trevor Blackwell, Michael D. Smith, and Brad Calder
- Appeared in the Workshop on Interaction between Compilers and Computer Architectures, San Antonio, Texas, Feb. 1997 Procedure Mapping Using Static Call Graph Estimation
- O C T O B E R 1 9 9 5 Research Report 95/6
- This paper appeared in the 28th Intl. Symp. on Microarchitecture A System Level Perspective on
- Next Cache Line and Set Prediction Brad Calder and Dirk Grunwald
- Reducing Branch Costs via Branch Alignment Brad Calder and Dirk Grunwald
- Fast & Accurate Instruction Fetch and Branch Prediction Brad Calder and Dirk Grunwald
- Leapfrogging: A Portable Technique for Implementing E cient David B. Wagner Bradley G. Calder
- Incorporating Predicate Information Into Branch Predictors Beth Simon Brad Calder Jeanne Ferrante
- UNIVERSITY OF CALIFORNIA, SAN DIEGO Reducing Load Delay to Improve Performance of Internet-Computing Programs
- UNIVERSITY OF CALIFORNIA, SAN DIEGO Turning Predicate Information to Advantage
- IEEE International Symposium on Performance Analysis of Systems and Software, March 2005 Motivation for Variable Length Intervals
- In Proceedings of the International Conference on Parallel Architectures and Compilation Techniques (PACT), Sept. 2005. An Event-Driven Multithreaded Dynamic Optimization Framework
- Exploiting a Computation Reuse Cache to Reduce Energy in Network Processors
- Exploiting Fine-Grained Data Parallelism with Chip Multiprocessors and Fast Barriers
- In proceedings of the International Conference on Parallel Architectures and Compilation Techniques, October 1999. Predicated Static Single Assignment
- Published in the International Journal of Parallel Programming, 2000. Path Analysis and Renaming for Predicated Instruction Scheduling
- Time Varying Behavior of Programs Timothy Sherwood Brad Calder
- UNIVERSITY OF CALIFORNIA, SAN DIEGO Value Pro ling for Instructions and Memory Locations
- Automatically Classifying Benign and Harmful Data Races Using Replay Analysis
- J. Parallel Distrib. Comput. 63 (2003) 597610 Entropia: architecture and performance of an enterprise
- Transient Fault Prediction Based on Anomalies in Processor Events
- In Proceedings of the 8th International Symposium on High Performance Computer Architecture (HPCA), February 2002. Quantifying Load Stream Behavior
- This paper appeared in the 2nd International Symposium on High Performance Computer Architecture, San Jose, February 1996. Predictive Sequential Associative Cache
- IEEE International Symposium on Performance Analysis of Systems and Software, March 2004 Structures for Phase Classification
- In Proceedings of the International Symposium on High Performance Distributed Computing (HPDC), August 2001. Reducing Delay With Dynamic Selection of Compression Formats
- To appear at the ACM SIGPLAN Conference on Programming Language Design and Implementation, June, 1997 E cient Procedure Mapping Using Cache Line Coloring
- In Proceedings of the International Symposium on Performance Analysis of Systems and Software (ISPASS 2006). Comparing Multinomial and K-Means Clustering for SimPoint
- Online Performance Auditing: Using Hot Optimizations Without Getting Burned
- Published in the Proceedings of the 26th International Symposium on Computer Architecture, May 1999. Selective Value Prediction
- Unbounded Page-Based Transactional Memory Weihaw Chuang, Satish Narayanasamy, Ganesh Venkatesh, Jack Sampson,
- Recording Shared Memory Dependencies Using Strata Satish Narayanasamy Cristiano Pereira Brad Calder
- UNIVERSITY OF CALIFORNIA, SAN DIEGO Compiler and Hardware Predicated Dependency Analysis and Scheduling.
- Efficient Sampling Startup for Sampled Processor Simulation
- The Precomputed Branch Architecture Brad Calder Dirk Grunwald
- In Proceedings of the 35th Annual International Symposium on Microarchitecture (MICRO-35), November 2002. Pointer Cache Assisted Prefetching
- The 11th International Conference on Parallel Architectures and Compilation Techniques (PACT), September 2002. Quantifying Instruction Criticality
- In Proceedings of the 7th International Symposium on High Performance Computer Architecture, January 2001. Dynamic Prediction of Critical Path Instructions
- Automated Design of Finite State Machine Predictors Timothy Sherwood Brad Calder
- This paper appeared in the Journal of Programming Languages, Vol 2, Num 4, 1994. Quantifying Behavioral Differences
- In Proceedings of the SIGPLAN Conference on Programming Language Design and Implementation (PLDI), June 2001. Using Annotations to Reduce Dynamic Optimization Time
- UNIVERSITY OF CALIFORNIA, SAN DIEGO Hardware Optimizations Enabled by a
- In Proceedings of the International Symposium on Computer Architecture, June 2005 BugNet: Continuously Recording Program Execution for
- A Decoupled Predictor-Directed Stream Prefetching Architecture Suleyman Sair Timothy Sherwood Brad Calder
- The Entropia Virtual Machine for Desktop Grids Brad Calder Andrew A. Chien Ju Wang Don Yang
- In Proceedings of the International Symposium on Code Generation and Optimization (CGO 2006). Selecting Software Phase Markers with Code Structure Analysis
- A Loop Correlation Technique to Improve Performance Auditing University of California, San Diego
- In Proceedings of the International Symposium on Performance Analysis of Systems and Software (ISPASS 2006). Considering All Starting Points for
- UNIVERSITY OF CALIFORNIA, SAN DIEGO Predictor-Directed Data Prefetching
- To appear in the Proc. of the ACM SIGPLAN Conf. on Prog. LanguageDesign and Implementation (PLDI '95), La Jolla, CA, June 1821, 1995 Corpus-based Static Branch Prediction
- Reducing Indirect Function Call Overhead In C++ Programs
- Debugging software is challenging because of the increasing complexity of soft-
- Journal of Instruction-Level Parallelism 1 (2000) 1-39 Submitted 5/99; published 5/00 A Comparative Survey of Load Speculation Architectures
- Software Profiling for Deterministic Replay Debugging of User Code
- Representative Multiprogram Workloads for Multithreaded Processor Simulation
- Journal of Instruction-Level Parallelism 1 (1999) 1-6 Submitted 6/98; published 3/99 Value Profiling and Optimization
- Dynamic Phase Analysis for Cycle-Close Trace Generation Cristiano Pereira Jeremy Lau Brad Calder Rajesh Gupta
- In Proceedings of the 37th International Symposium on Microarchitecture, December, 2004 Balanced Multithreading: Increasing Throughput via a
