- A Timing-constrained Simultaneous Global Routing Algorithm Jiang Hu and Sachin S. Sapatnekar
- Optimizing Large Multi-Phase Level-Clocked Circuits Naresh Maheshwari and Sachin S. Sapatnekar
- Efficient PEEC-based Inductance Extraction using Circuit-Aware Techniques Haitian Hu and Sachin S. Sapatnekar
- Thermal Via Placement in 3D ICs Brent Goplen
- Early-stage Power Grid Analysis for Uncertain Working Modes
- Convexity-based Algorithms for Design Centering Sachin S. Sapatnekar, Pravin M. Vaidya and Sung-Mo Kang
- E cient Minarea Retiming of Large Level-Clocked Circuits Naresh Maheshwari Sachin S. Sapatnekar
- Statistical Leakage Estimation of Double Gate FinFET Devices Considering the Width Quantization Property
- A Framework for Block-Based Timing Sensitivity Analysis Sanjay V. Kumar
- Random Walks in a Supply Network Haifeng Qian
- Adaptive Techniques for Overcoming Performance Degradation due to Aging in Digital Circuits
- Electrothermal Analysis and Optimization Techniques for Nanoscale Integrated Circuits
- Exact lower bound for the number of switches in series to implement a combinational logic cell
- Wiresizing with Bu er Placement and Sizing for Power-Delay Tradeo s
- Buffering Global Interconnects in Structured ASIC Tianpei Zhang and Sachin S. Sapatnekar
- POWER ESTIMATION CONSIDERING STATISTICAL IC PARAMETRIC Sabita Pilli Sachin S. Sapatnekar
- Capturing the Effect of Crosstalk on Delay Sachin S. Sapatnekar
- Technology Mapping for Domino Logic Min Zhao Sachin S. Sapatnekar
- A Graph-theoretic Approach to Clock Skew Optimization Rahul B. Deokar and Sachin S. Sapatnekar
- Dual-monotonic domino gate mapping and optimal output phase assignment of domino logic Min Zhao Sachin S. Sapatnekar
- A Progressive-ILP Based Routing Algorithm for Cross-Referencing Biochips
- RC Interconnect Optimization under the Elmore Delay Model Sachin S. Sapatnekar
- Timing-driven Partitioning for Two-Phase Domino and Mixed Static/Domino Implementations Min Zhao and Sachin S. Sapatnekar
- Full-Chip Analysis of Leakage Power Under Process Variations, Including Spatial Correlations
- Efficient Thermal Placement of Standard Cells in 3D ICs using a Force Directed Approach
- LOW POWER CLOCK DISTRIBUTION USING MULTIPLE VOLTAGES AND REDUCED SWINGS1
- Physical Design Automation Challenges for 3D ICs Sachin S. Sapatnekar
- A High Efficiency Full-Chip Thermal Simulation Algorithm Yong Zhan and Sachin S. Sapatnekar
- A general model for performance optimization of sequential systems
- MINFLOTRANSIT: MIN-COST FLOW BASED TRANSISTOR SIZING TOOL Vijay Sundararajan, Sachin S. Sapatnekar, Keshab K. Parhi
- On the Selection of On-Chip Inductors for the Optimal VCO Design Yong Zhan, Ramesh Harjani, and Sachin S. Sapatnekar
- Foundations and Trends R Electronic Design Automation
- Automated Module Assignment in Stacked-Vdd Designs for High-Efficiency Power Delivery
- Body Bias Voltage Computations for Process and Temperature Compensation
- A Geometric Programming-based Worst-Case Gate Sizing Method Incorporating Spatial Correlation
- Technology Mapping Using Logical Effort Solving the Load Distribution Problem
- Simultaneous Shield and Buffer Insertion for Crosstalk Noise Reduction in Global Routing
- Closed formed expressions for buffered interconnect delay approximation have been around for some time. However, pre-
- A Partition-based Algorithm for Power Grid Design using Locality
- Fast Comparisons of Circuit Implementations Shrirang K. Karandikar and Sachin S. Sapatnekar, Fellow, IEEE
- Placement and Routing in 3D Integrated Circuits Cristinel Ababei, Yan Feng, Brent Goplen, Hushrav Mogal,
- IEEE TRANSACTIONS ON COMPUTER-AIDED DESIGN OF INTEGRATED CIRCUITS AND SYSTEMS, VOL. , NO. , 1 Early-stage Power Grid Analysis for Uncertain
- Optimal Decoupling Capacitor Sizing and Placement for Standard Cell Layout Designs
- Fast On-chip Inductance Simulation using a Precorrected-FFT Method Haitian Hu, ECE Department, University of Minnesota, Minneapolis, MN 55455
- Efficient Inductance Extraction using Circuit-Aware Techniques Haitian Hu and Sachin S. Sapatnekar
- C. J. Alpert1 , G. Gandham1
- Technology Mapping for High Performance Static CMOS and Pass Transistor Logic Designs
- A Timing Model Incorporating the E ect of Crosstalk on Delay and its Application to Optimal Channel Routing
- Power-Delay Optimizations in Gate Sizing 1 Sachin S. Sapatnekar
- Retiming Control Logic Naresh Maheshwari Sachin S. Sapatnekar
- Interleaving Bu er Insertion and Transistor Sizing into a Single Optimization
- An Algorithm for Simulating Power Ground Networks using Pad e Approximants and its Symbolic Implementation
- A Framework for Exploiting Data and Functional Parallelism on Distributed Memory Multicomputers
- Wire Sizing as a Convex Optimization Problem: Exploring the Area-Delay Tradeo
- Timing and Area Optimization for Standard-Cell VLSI Circuit Design 1
- Synthesizing a Representative Critical Path for Post-Silicon Delay Prediction
- Addressing Thermal and Power Delivery Bottlenecks in 3D Circuits Sachin S. Sapatnekar
- Congestion-Aware Power Grid Optimization for 3D Circuits Using MIM and CMOS Decoupling Capacitors
- Reliable Power Delivery for 3D ICs Pingqiang Zhou
- CAD for 3D Circuits: Solutions and Challenges Sachin S. Sapatnekar
- Placement of 3D ICs with Thermal and Interlayer Via Considerations Brent Goplen*
- Width-dependent Statistical Leakage Modeling for Random Dopant Induced Threshold Voltage Shift
- Temperature-Aware Floorplanning of Microarchitecture Blocks with IPC-Power Dependence Modeling and
- Temperature-Aware Routing in 3D ICs Tianpei Zhang, Yong Zhan, and Sachin S. Sapatnekar
- A Hybrid Linear Equation Solver and its Application in Quadratic Placement
- Net Weighting to Reduce Repeater Counts during Placement Brent Goplen*
- An Efficient Technology Mapping Algorithm Targeting Routing Congestion under Delay Constraints
- Buffering Global Interconnects in Structured ASIC Design Tianpei Zhang and Sachin S. Sapatnekar
- Closed formed expressions for buffered interconnect delay approximation have been around for some time. However,
- TOPOLOGY OPTIMIZATION OF STRUCTURED POWER/GROUND NETWORKS Jaskirat Singh Sachin S. Sapatnekar
- Optimization of Integrated Spiral Inductors Using Sequential Quadratic Programming
- Hierarchical Random-walk Algorithms for Power Grid Analysis
- HIGH-PERFORMANCE POWER GRIDS FOR NANOMETER TECHNOLOGIES Sachin S. Sapatnekar
- STATISTICAL TIMING ANALYSIS CONSIDERING SPATIAL CORRELATIONS USING A SINGLE PERT-LIKE TRAVERSAL
- An Efficient Algorithm for Calculating the Worst-case Delay due to Crosstalk Venkatesan Rajappan, Synplicity Inc., Sunnyvale, CA 94086
- Table Look-up Based Compact Modeling for On-chip Interconnect Timing and Noise Analysis
- A Precorrected-FFT Method for Simulating On-chip Inductance Haitian Hu, ECE Department, University of Minnesota, Minneapolis, MN 55455
- An Efficient Algorithm for Low Power Pass Transistor Logic Synthesis Rupesh S. Shelar, Sachin S. Sapatnekar
- Hybrid Structured Clock Network Construction1 Haihua Su Sachin S. Sapatnekar
- Circuit-Aware On-chip Inductance Extraction Haitian Hu and Sachin S. Sapatnekar
- Convexity-Based Optimization for Power-Delay Tradeoff using Transistor Sizing Mahesh Ketkar, and Sachin S. Sapatnekar
- Fast Analysis and Optimization of Power/Ground Networks Haihua Su Kaushik H. Gala Sachin S. Sapatnekar
- Convex Delay Models for Transistor Sizing Mahesh Ketkar
- Hierarchical Analysis of Power Distribution Networks Min Zhao, Rajendran V. Panda, Sachin S. Sapatnekar, Tim Edwards, Rajat Chaudhry, David Blaauw
- On the Chicken-and-Egg Problem of Determining the E ect of Crosstalk on Delay in Integrated Circuits
- Clock Distribution Using Multiple Voltages Jatuchai Pangjun and Sachin S. Sapatnekar
- FAR-DS: Full-plane AWE Routing with Driver Sizing Jiang Hu and Sachin S. Sapatnekar
- Routing Tree Topology Construction to Meet Interconnect Timing Constraints
- Combined Transistor Sizing with Bu er Insertion for Timing Optimization
- Retiming Level-Clocked Circuits for Latch Count Minimization
- An Improved Algorithm for Minimum-Area Retiming Naresh Maheshwari and Sachin S. Sapatnekar
- SYMBOLIC ANALYSIS OF POWER GROUND NETWORKS USING MOMENT-MATCHING METHODS
- (buffering) Circuit No. Trans Clock
- Clock Tree Synthesis For Multi-Chip Modules1 Daksh Lehther and Sachin S. Sapatnekar
- Speeding up Pipelined Circuits through a Combination of Gate Sizing and Clock Skew Optimization
- Layout Optimization Using Arbitrarily High Degree Posynomial Models Piyush K. Sanchetiy and Sachin S. Sapatnekarz
- Convexity-based Algorithms for Design Centering Sachin S: Sapatnekary
- Feasible Region Approximation Using Convex Polytopes Sachin S: Sapatnekar Pravin M: Vaidya S: M: Kang
- Module Assignment for Pin-Limited Designs under the Stacked-Vdd Paradigm Yong Zhan, Tianpei Zhang, and Sachin S. Sapatnekar
- Stack Sizing for Optimal Current Drivability in Subthreshold Circuits
- A Practical Algorithm for Retiming Level-Clocked Circuits1 Naresh Maheshwari Sachin S. Sapatnekar
- A Survey on Multi-net Global Routing for Integrated Circuits Jiang Hu and Sachin S. Sapatnekar
- Placement of Thermal Vias in 3D ICs using Various Thermal Objectives
- Speeding up Pipelined Circuits through a Combination of Gate Sizing and Clock Skew Optimization
- E cient Retiming of Large Circuits Naresh Maheshwari, Student Member, IEEE, and Sachin Sapatnekar, Member, IEEE
- Fast Computation of the Temperature Distribution in VLSI Chips Using the Discrete Cosine Transform and Table Look-up
- Datapath Routing Based on a Decongestion Metric Suresh Raman
- A Fast Algorithm for Power Grid Design Jaskirat Singh Sachin S. Sapatnekar
- Proc. IEEE 1993 Custom Integrated Circuits Conf. DELAY AND AREA OPTIMIZATION FOR DISCRETE GATE SIZES
- NonHanan Routing Huibo Hou, Jiang Hu and Sachin S. Sapatnekar
- STOCHASTIC PRECONDITIONING FOR DIAGONALLY DOMINANT MATRICES
- Fast Comparisons of Circuit Implementations Shrirang K. Karandikar and Sachin S. Sapatnekar
- Statistical Timing Analysis with Correlated Non-Gaussian Parameters using Independent Component Analysis
- Application of Symbolic Analysis to Power and Ground Interconnect Optimization
- Efficient Layout Synthesis Algorithm for Pass Transistor Logic Circuits Rupesh S. Shelar and Sachin S. Sapatnekar
- Analysis and Optimization of Structured Power/Ground Networks
- Optimal Design of Macrocells for Low Power and High Speed
- A Fresh Look at Retiming via Clock Skew Optimization Rahul B. Deokar and Sachin S. Sapatnekar
- Designing optimized pipelined global interconnects: Algorithms and methodology impact
- An Analytical Model for Negative Bias Temperature Instability Sanjay V. Kumar, Chris H. Kim, and Sachin S. Sapatnekar
- Logical Effort Based Technology Mapping Shrirang K. Karandikar
- E cient Calculation of All-Pairs Input-to-Output Delays in Synchronous Sequential Circuits
- Congestion-aware Topology Optimization of Structured Power/Ground Networks
- A Uni ed Algorithm for Gate Sizing and Clock Skew Optimization to Minimize Sequential Circuit Area
- Interconnect Design Using Convex Optimization Piyush K. Sancheti and Sachin S. Sapatnekar
- Minimum Area Retiming with Equivalent Initial States 1 Naresh Maheshwari Sachin S. Sapatnekar
- A Scalable Statistical Static Timing Analyzer Incorporating Correlated Non-Gaussian and
- Technology Mapping Targeting Routing Congestion under Delay Constraints
- A Method for Correcting the Functionality of a Wire-Pipelined Circuit
- Confidence Scalable Post-Silicon Statistical Delay Prediction under Process Variations
- Robust Gate Sizing by Geometric Programming Jaskirat Singh Vidyasagar Nookala Zhi-Quan Luo Sachin Sapatnekar
- Temperature-Aware Placement for SOCs Charlie Chung-Ping Chen, Jeng-Liang Tsai, Guoqiang Chen, Brent Goplen, Haifeng Qian, Yong Zhan,
- Technology Mapping Algorithms for Domino Logic Advanced Tools, Motorola Inc., Austin, Texas, 78729
- Moment-based techniques for RLC clock tree construction Daksh Lehther and Sachin S. Sapatnekar
- The dominating contribution of interconnect to system per-formance has made it critical to plan for buffer and wiring
- Gate Size Optimization for Row-based Layouts Naresh Maheshwari Sachin S. Sapatnekar
- An Integrated Algorithm for Combined Placement and Libraryless Technology Mapping
- IEEE TRANSACTIONS ON VLSI SYSTEMS, VOL. XX, NO. XX, XX 2005 1 BDD Decomposition for Delay Oriented
- Power vs. Delay in Gate Sizing: Con icting Objectives? Sachin S. Sapatnekar Weitong Chuang
- IEEE TRANSACTIONS ON COMPUTER-AIDED DESIGN OF INTEGRATED CIRCUITS AND SYSTEMS, VOL. 24, NO. 4, APRIL 2005 1 A Predictive Distributed Congestion Metric With
- To appear in the Proceedings of the International Conference on Parallel Processing '94 1 A Convex Programming Approach for Exploiting Data and Functional
- A Methodology for the Simultaneous Design of Supply and Signal Networks
- Transistor and Pin Reordering for Gate Oxide Leakage Reduction in Dual Tox Circuits
- Technology Mapping for SOI Domino Logic Incorporating Solutions for the Parasitic Bipolar
- A Predictive Distributed Congestion Metric and its Application to Technology Mapping
- Algorithms for Non-Hanan-based Optimization for VLSI Interconnect under a Higher Order AWE Model
- TITLE : Probability-driven Routing in a Datapath Environment For a four-layer datapath routing environment, we present an algorithm that considers all the nets
- A Chip-level Electrostatic Discharge Simulation Strategy Haifeng Qian
- Probabilistic Congestion Prediction with Partial Blockages , Charles J. Alpert1
- A Fast Global Gate Collapsing Technique for High Performance Designs using Static CMOS and Pass Transistor Logic
- Efficient Crosstalk Estimation Martin Kuhlmann, Sachin S. Sapatnekar, Keshab K. Parhi
- MARSH:MIN-AREA RETIMING WITH SETUP AND HOLD CONSTRAINTS Vijay Sundararajan, Sachin S. Sapatnekar, Keshab K. Parhi
- A Fixed-die Floorplanning Algorithm Using an Analytical Approach Yong Zhan, Yan Feng, and Sachin S. Sapatnekar
- SIMULTANEOUS BUFFER INSERTION AND NON-HANAN OPTIMIZATION FOR VLSI INTERCONNECT UNDER A HIGHER ORDER AWE MODEL
- Simultaneous Shield and Buffer Insertion for Crosstalk Noise Reduction in Global Routing
- Timing Optimization of Mixed Static and Domino Logic Min Zhao Sachin S. Sapatnekar
- Utilizing the Retiming-Skew Equivalence in a Practical Algorithm for Retiming Large Circuits
- IEEE TRANSACTIONS ON COMPUTER-AIDED DESIGN OF INTEGRATED CIRCUITS AND SYSTEMS, VOL. , NO. , 1 Power Grid Analysis using Random Walks
- Statistical Timing Analysis Under Spatial Correlations
- Tradeoffs between Gate Oxide Leakage and Delay for Dual ToxToxTox Circuits
- An Exact Solution to the Transistor Sizing Problem for CMOS Circuits Using Convex Optimization
- Gate Oxide Leakage and Delay Tradeoffs for Dual Circuits Anup Kumar Sultania, Dennis Sylvester, and Sachin S. Sapatnekar
- Prediction of Leakage Power Under Process Uncertainties
- DAG Based Library-Free Technology Mapping F. S. Marques1
- Fast Estimation of Area-Delay Trade-offs in Circuit Sizing Sizing a circuit can improve performance drastically. However, this
- Partition-Driven Standard Cell Thermal Placement Guoqiang Chen
- High Efficiency Green Function-Based Thermal Simulation Algorithms Yong Zhan and Sachin S. Sapatnekar, Fellow, IEEE
- Exploration of On-Chip Switched-Capacitor DC-DC Converter for Multicore Processors Using a Distributed Power Delivery
- Adaptive Techniques for Overcoming Performance Degradation due to Aging in CMOS Circuits
- Accounting for Inherent Circuit Resilience and Process Variations in Analyzing Gate Oxide Reliability
- Overcoming Variations in Nanometer-Scale Technologies
- NoC Frequency Scaling with Flexible-Pipeline Routers Pingqiang Zhou, Jieming Yin, Antonia Zhai and Sachin S. Sapatnekar
- Dummy Fill Optimization for Enhanced Manufacturability Yaoguang Wei and Sachin S. Sapatnekar
- IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS 1 Scalable Methods for Analyzing the Circuit Failure
- IEEE TRANSACTIONS ON COMPUTER-AIDED DESIGN OF INTEGRATED CIRCUITS AND SYSTEMS, VOL. XX, NO. Y, MONTH 2009 1 A Progressive-ILP Based Routing Algorithm for the
- Fast Poisson Solvers for Thermal Analysis Haifeng Qian
- Power Grid Optimization in 3D Circuits Using MIM and CMOS Decoupling Capacitors
- A Framework for Scalable Post-Silicon Statistical Delay Prediction under Spatial Variations
- A Finite-Oxide Thickness Based Analytical Model for Negative Bias Temperature Instability
- Capturing Post-Silicon Variations using a Representative Critical Path
- Scalable Methods for the Analysis and Optimization of Gate Oxide Breakdown Jianxin Fang, Sachin S. Sapatnekar
- IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS 1 Compact Current Source Models
- Thermal Signature: A Simple Yet Accurate Thermal Index for Floorplan Optimization
- Enabling Improved Power Management in Multicore Processors through Clustered DVFS
- A Scaled Random Walk Solver for Fast Power Grid Analysis Baktash Boghrati, Sachin Sapatnekar
