Friedman, Eby G. - Department of Electrical and Computer Engineering, University of Rochester

• On-Chip Power Noise Reduction Techniques in High Performance SoC-Based Integrated Circuits
• 762 IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS, VOL. 10, NO. 6, DECEMBER 2002 Inductive Properties of High-Performance
• J. Low Power Electron. Appl. 2011, 1, 219-246; doi:10.3390/jlpea1010219 Low Power Electronics
• Noise Estimation Due To Signal Activity For Capacitively Coupled CMOS Logic Gates
• 184 IEEE TRANSACTIONS ON COMPUTER-AIDED DESIGN OF INTEGRATED CIRCUITS AND SYSTEMS, VOL. 21, NO. 2, FEBRUARY 2002 Retiming and Clock Scheduling for Digital Circuit
• IMPEDANCE CHARACTERISTICS OF DECOUPLING CAPACITORS IN MULTI-POWER DISTRIBUTION SYSTEMS
• 2010 IEEE 26-th Convention of Electrical and Electronics Engineers in Israel 978-1-4244-8682-3/10/$26.00 2010 IEEE
• Optimal Clock Skew Scheduling Tolerant to Process Variations Jos Luis Neves and Eby G. Friedman
• Supported by Technion Advanced Circuit Research Lab (ACRC) Efficiency Optimization of Integrated DC-DC Buck Converters
• IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS, VOL. 13, NO. 8, AUGUST 2005 971 Transactions Briefs__________________________________________________________________
• 26 IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS--II: EXPRESS BRIEFS, VOL. 55, NO. 1, JANUARY 2008 Effective Capacitance of Inductive Interconnects for
• 498 IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS--II: ANALOG AND DIGITAL SIGNAL PROCESSING, VOL. 44, NO. 6, JUNE 1997 A Comparison of Analog and Digital Circuit
• Via Placement for Minimum Interconnect Delay in Three-Dimensional (3-D) Circuits
• Optimizing Inductive Interconnect for Low Power Magdy A. El-Moursy and Eby G. Friedman
• Author's personal copy Thermal analysis of oxide-confined VCSEL arrays$
• 164 IEEE PHOTONICS TECHNOLOGY LETTERS, VOL. 23, NO. 3, FEBRUARY 1, 2011 A 3-D Integrated Intrachip Free-Space Optical
• IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS, VOL. 18, NO. 5, MAY 2010 689 Unified Logical Effort--A Method for Delay
• 1262 IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS, VOL. 18, NO. 8, AUGUST 2010 Corrections to "Unified Logical Effort--A Method for
• IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS, VOL. 17, NO. 10, OCTOBER 2009 1559 Fig. 6. Waveforms of h0r0; 1r1=1=0i simulation (Df4).
• IEEE TRANSACTIONS ON ELECTRON DEVICES, VOL. 56, NO. 9, SEPTEMBER 2009 1873 Closed-Form Expressions of 3-D Via Resistance,
• IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS--II: EXPRESS BRIEFS, VOL. 56, NO. 7, JULY 2009 585 Inductance Model of Interdigitated Power and
• IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS--I: REGULAR PAPERS, VOL. 56, NO. 5, MAY 2009 997 Worst Case Power/Ground Noise Estimation Using
• IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS, VOL. 17, NO. 2, FEBRUARY 2009 181 Quasi-Resonant Interconnects: A Low Power, Low
• IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS, VOL. 16, NO. 12, DECEMBER 2008 1717 perimental results show that BPDG-based substrate noise estimation
• This article appeared in a journal published by Elsevier. The attached copy is furnished to the author for internal non-commercial research
• IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS, VOL. 15, NO. 10, OCTOBER 2007 1081 3-D Topologies for Networks-on-Chip
• IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS, VOL. 15, NO. 2, FEBRUARY 2007 135 Design Methodology for Global Resonant H-Tree
• IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS, VOL. 14, NO. 6, JUNE 2006 641 [1] P. Larsson and C. Svensson, "Noise in digital dynamic CMOS circuits,"
• IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS, VOL. 14, NO. 2, FEBRUARY 2006 161 Low-Power Repeaters Driving RC and RLC
• 396 IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS, VOL. 13, NO. 3, MARCH 2005 Transactions Briefs__________________________________________________________________
• IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS, VOL. 12, NO. 12, DECEMBER 2004 1295 Power Characteristics of Inductive Interconnect
• 1148 IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS, VOL. 12, NO. 11, NOVEMBER 2004 Impedance Characteristics of Power Distribution
• Analog Integrated Circuits and Signal Processing, 41, 511, 2004 c 2004 Kluwer Academic Publishers. Manufactured in The Netherlands.
• IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS--II: EXPRESS BRIEFS, VOL. 51, NO. 5, MAY 2004 241 Low-Voltage-Swing Monolithic dcdc Conversion
• IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS, VOL. 12, NO. 5, MAY 2004 485 Sleep Switch Dual Threshold Voltage Domino Logic
• 514 IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS, VOL. 11, NO. 3, JUNE 2003 [7] , "On optimal board-level routing for FPGA-based logic emula-
• Journal of Circuits, Systems, and Computers Vol. 12, No. 1 (2003) 3140
• Journal of Circuits, Systems, and Computers, Vol. 11, No. 3 (2002) 231245 c World Scientific Publishing Company
• Analog Integrated Circuits and Signal Processing, 28, 253264, 2001 C 2001 Kluwer Academic Publishers. Manufactured in The Netherlands.
• Analog Integrated Circuits and Signal Processing, 27, 275279, 2001 C 2001 Kluwer Academic Publishers. Manufactured in The Netherlands.
• Clock Distribution Networks in Synchronous Digital Integrated Circuits
• IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS, VOL. 8, NO. 2, APRIL 2000 195 Effects of Inductance on the Propagation Delay and
• 442 IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS, VOL. 7, NO. 4, DECEMBER 1999 Figures of Merit to Characterize the Importance
• IEEE TRANSACTIONS ON APPLIED SUPERCONDUCTIVITY, VOL. 9, NO. 3, SEPTEMBER 1999 4591 Toward a Systematic Design Methodology for Large
• 18 IEEE TRANSACTIONS ON APPLIED SUPERCONDUCTIVITY, VOL. 9, NO. 1, MARCH 1999 Tools for the Computer-Aided Design
• IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS--II: ANALOG AND DIGITAL SIGNAL PROCESSING, VOL. 45, NO. 5, MAY 1998 607 Repeater Design to Reduce Delay and Power
• 656 IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS--II: ANALOG AND DIGITAL SIGNAL PROCESSING, VOL. 44, NO. 8, AUGUST 1997 Transactions Briefs
• IEEE JOURNAL OF SOLID-STATE CIRCUITS, VOL. 30, NO. 2, FEBRUARY 1995 151 Design of Tapered Buffers with Local Interconnect Capacitance
• Shahar Kvatinsky* , Eby G. Friedman**
• Simultaneous Co-Design of Distributed On-Chip Power Supplies and Decoupling Capacitors
• Fast Algorithms for Power Grid Analysis Based on Effective Resistance
• Compact Substrate Models For Efficient Noise Coupling and Signal Isolation Analysis
• Globally Integrated Power and Clock Distribution Network
• On-Chip Point-of-Load Voltage Regulator for Distributed Power Supplies
• Minimizing Noise via Shield and Repeater Insertion Renatas Jakushokas and Eby G. Friedman
• Contact Merging Algorithm for Efficient Substrate Noise Analysis in Large Scale Circuits
• Power Efficient Tree-Based Crosslinks for Skew Reduction Inna Vaisband, Ran Ginosar, Avinoam Kolodny
• Simultaneous Shield and Repeater Insertion Renatas Jakushokas
• Clock Distribution Architectures for 3-D SOI Integrated Circuits Vasilis F. Pavlidis, Ioannis Savidis, and Eby G. Friedman
• Physical Design for Reduced Delay Uncertainty in High Performance Clock Distribution Networks
• A Higher-Order Mismatch-Shaping Method for Multi-Bit Sigma-Delta Modulators
• Transient Simulation of On-Chip Transmission Lines via Exact Pole Extraction
• Electrical Modeling and Characterization of 3-D Vias Ioannis Savidis and Eby G. Friedman
• On-Chip Optical Interconnect for Reduced Delay Uncertainty
• Abstract --Design and analysis guidelines for resonant interconnect networks are presented in this paper. The
• Low Power Quasi-Resonant Interconnects Jonathan Rosenfeld and Eby G. Friedman
• Substrate and Ground Noise Interactions in Mixed-Signal Circuits
• 3-D Topologies for Networks-on-Chip Vasilis F. Pavlidis and Eby G. Friedman
• Optimum Wire Tapering for Minimum Power Dissipation in RLC Interconnects
• Sensitivity Evaluation of Global Resonant H-Tree Clock Distribution Networks
• Pessimism Reduction In Static Timing Analysis Using Interdependent Setup and Hold Times
• Leveraging Symbiotic On-Die Decoupling Capacitance Michael Sotman Mikhail Popovich Avinoam Kolodny Eby Friedman
• On-chip Optical Interconnect Roadmap: Challenges and Critical Directions Mikhail Haurylau, Hui Chen, Jidong Zhang, Guoqing Chen, Nicholas A. Nelson,
• Low Power Repeaters Driving RLC Interconnects with Delay and Bandwidth Constraints
• Predictions of CMOS Compatible On-Chip Optical Interconnect
• Noise Aware Decoupling Capacitors for Multi-Voltage Power Distribution Systems
• A 250 MHZ DELTA-SIGMA MODULATOR FOR LOW COST ULTRASOUND/SONAR BEAMFORMING
• Low Power Repeaters Driving Interconnects with
• LOW POWER FLEXIBLE RAKE RECEIVERS FOR WCDMA Boris D. Andreev, Edward L. Titlebaum, and Eby G. Friedman
• of Shield Insertion on Reducing Crosstalk Noise between Coupled Interconnects Junmou Zhang and Eby G. Friedman
• A Low Power Thyristor-Based CMOS Programmable Delay Element Junmou Zhang
• *This research was supported in part by a grant from Intel Corporation. Department of Electrical and Computer Engineering
• INDUCTIVE INTERCONNECT WIDTH OPTIMIZATION FOR LOW POWER
• Managing Static Leakage Energy in Microprocessor Functional Units Steven Dropsho, Volkan Kursun, David H. Albonesi,
• Efficiency Analysis of a High Frequency Buck Converter for On-Chip Integration with a Dual-VDD Microprocessor
• Domino Logic with Dynamic Body Biased Keeper Volkan Kursun and Eby G. Friedman
• Properties of On-Chip Inductive Current Loops Andrey V. Mezhiba and Eby G. Friedman
• Transient Analysis of a CMOS Inverter Driving Resistive Interconnect Kevin T. Tang and Eby G. Friedman
• Estimation of On-Chip Simultaneous Switching Noise in VDSM CMOS Circuits Kevin T. Tang and Eby G. Friedman
• Transparent Repeaters 1 Radu M. Secareanu and Eby G. Friedman
• Clock Skew Scheduling for Improved Reliability via Quadratic Programming Ivan S. Kourtev and Eby G. Friedman
• A HIGH PRECISION CMOS CURRENT MIRROR / DIVIDER Radu M. Secareanu and Eby G. Friedman
• Department of Electrical Engineering University of Roche&r
• ANALOG VS. DIGITAL: A COMPARISON OF CIRCUIT IMPLEMENTATIONS FOR LOW-POWER MATCHED FILTERS
• On-Chip Power Delivery Inna Vaisband, Selcuk Kose, Ioannis Savidis, Jonathan Rosenfeld, and Eby G. Friedman
• Eby G. Friedman University of Rochester
• Keynote Speech 1 Keynote Speaker: Prof. Eby G. Friedman
• Volume 10, Number 3, September/October 1999 ISSN 1049-3654 THE INSTITUTE OF
• Noise Immunity of Digital Circuits in Mixed-Signal Smart Power Systems Radu M. Secareanu, Ivan S. Kourtev, Juan Becerra
• 950 IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS--I: FUNDAMENTAL THEORY AND APPLICATIONS, VOL. 46, NO. 8, AUGUST 1999 Dynamic and Short-Circuit Power of CMOS
• Low Swing Dual Threshold Voltage Domino Logic Volkan Kursun and Eby G. Friedman
• 474 CLOCK DISTRIBUTION IN SYNCHRONOUS SYSTEMS CLOCK DISTRIBUTION IN
• On-Chip DC-DC Converters for Three-Dimensional ICs Jonathan Rosenfeld and Eby G. Friedman
• 742 IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS, VOL. 18, NO. 5, MAY 2010 Resource Based Optimization for Simultaneous
• Analog Integrated Circuits and Signal Processing, 42, 231238, 2005 c 2005 Springer Science + Business Media, Inc. Manufactured in The Netherlands.
• INTEGRATION, the VLSI journal 29 (2000) 131}165 Delay and noise estimation of CMOS logic gates driving
• INTEGRATION, the VLSI journal 40 (2007) 461472 Wire shaping of RLC interconnects$
• Peak Noise Prediction in Loosely Coupled Interconnect Kevin T. Tang and Eby G. Friedman
• NODE VOLTAGE DEPENDENT SUBTHRESHOLD LEAKAGE CURRENT CHARACTERISTICS OF DYNAMIC CIRCUITS
• IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS, VOL. 12, NO. 1, JANUARY 2004 67 Substrate Coupling in Digital Circuits in Mixed-Signal
• EXPONENTIALLY TAPERED H-TREE CLOCK DISTRIBUTION NETWORKS Magdy A. El-Moursy and Eby G. Friedman
• Dominant Substrate Noise Coupling Mechanism for Multiple Switching Gates
• Shielding Methodologies in the Presence of Power/Ground Noise
• Maximizing Performance by Retiming and Clock Skew Scheduling Xun Liu Marios C. Papaefthymiou
• Effects of Inductance on the Propagation Delay and Repeater Insertion in VLSI Circuits
• Design Challenges in High Performance Three-Dimensional Circuits
• DESIGN AND SIMULATION OF FRACTIONAL-N PLL FREQUENCY SYNTHESIZERS
• Decoupling Capacitors for Power Distribution Systems with Multiple Power Supply Voltages
• Power Grid Noise in TSV-Based 3-D Integrated Systems Ioannis Savidis, Selcuk Kose, and Eby G. Friedman
• 170 IEEE TRANSACTIONS ON COMPUTER-AIDED DESIGN OF INTEGRATED CIRCUITS AND SYSTEMS, VOL. 24, NO. 2, FEBRUARY 2005 An RLC Interconnect Model Based on
• On-die Decoupling Capacitance: Frequency Domain Analysis ofActivity Radius
• Equivalent Rise Time for Resonance in Power/Ground Noise Estimation
• Initial Results of Prototyping a 3-D Integrated Intra-Chip Free-Space Optical Interconnect
• Delay and Power Expressions Characterizing a CMOS Inverter Driving an Kevin T. Tang and Eby G. Friedman
• Effective Capacitance of RLC Loads for Estimating Short-Circuit Power
• IEEE TRANSACTIONS ON COMPUTER-AIDED DESIGN OF INTEGRATED CIRCUITS AND SYSTEMS, VOL. 21, NO. 2, FEBRUARY 2002 131 DTT: Direct Truncation of the Transfer Function--An
• 1114 IEEE TRANSACTIONS ON COMPUTER-AIDED DESIGN OF INTEGRATED CIRCUITS AND SYSTEMS, VOL. 26, NO. 6, JUNE 2007 Exploiting SetupHold-Time Interdependence in
• Peak Crosstalk Noise Estimation in CMOS VLSI Circuits Kevin T. Tang and Eby G. Friedman
• TimingDriven VariationAware Nonuniform Clock Mesh Ameer Abdelhadi, Ran Ginosar, Avinoam Kolodny, and Eby G. Friedman
• INTEGRATION, the VLSI journal 40 (2007) 434446 Predictions of CMOS compatible on-chip optical interconnect$
• Challenges in Ultra Deep Submicrometer High Performance VLSI Circuits Professor Eby G. Friedman
• Two-phase Clocking for Medium to Large RSFQ Circuits Kris Gaj, Eby G. Friedman, and Marc J.Feldman
• Journal of Circuits, Systems, and Computers Vol. 15, No. 3 (2006) 437454
• Analog Integrated Circuits and Signal Processing, 44, 271281, 2005 c 2005 Springer Science + Business Media, Inc. Manufactured in The Netherlands.
• A BULK-DRIVEN CMOS OTA WITH 68 dB DC GAIN Jonathan Rosenfeld, Mcahit Kozak, and Eby G. Friedman
• Exploiting Hysteresis in a CMOS Bu er Radu M. Secareanu, Victor Adler, and Eby G. Friedman
• Scaling Trends of On-Chip Power Distribution Noise Andrey V. Mezhiba and Eby G. Friedman
• Repeater Insertion in Tree Structured Inductive Interconnect Yehea I. Ismail, Eby G. Friedman, and Jose L. Neves1
• Signal Waveform Characterization in RLC Trees Yehea I. Ismail, Eby G. Friedman, and Jose L. Neves1
• IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS--II: ANALOG AND DIGITAL SIGNAL PROCESSING, VOL. 48, NO. 5, MAY 2001 471 Repeater Insertion in Tree Structured
• IEEE TRANSACTIONS ON COMPUTER-AIDED DESIGN OF INTEGRATED CIRCUITS AND SYSTEMS, VOL. 19, NO. 1, JANUARY 2000 83 Equivalent Elmore Delay for RLC Trees
• Reduced Delay Uncertainty in High Performance Clock Distribution Networks Dimitrios Velenis
• IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS, VOL. 14, NO. 3, MARCH 2006 217 Decoupling Capacitors for Multi-Voltage Power
• Keynote Speakers "Interconnect-Based Design Challenges in High Performance Two-and Three-
• Performance Criteria for Evaluating the Importance of On-Chip Inductance Yehea I. Ismail, Eby G. Friedman, and Jose L. NevesL
• Timing Optimization in Logic with Interconnect Morgenshtein
• Physical Design to Improve the Noise Immunity of Digital Circuits in a Mixed-Signal Smart-Pow er System Radu M. Secareanu, Scott Warner , Scott Seabridge , Cathie Burke ,
• Crosstalk Noise Model for Shielded Interconnects in VLSI-based Circuits Junmou Zhang and Eby G. Friedman
• Optimum Wire Shaping of an Interconnect
• A Hybrid Radix-4/Radix-8 LOWPower, High Speed Multiplier Architecture for Wide Bit Widths
• Orthogonal Code Generator for 3G Wireless Transceivers Boris D. Andreev, Edward L. Titlebaum, and Eby G. Friedman
• Efficient Placement of Distributed On-Chip Decoupling Capacitors in Nanoscale ICs
• 894 IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS, VOL. 16, NO. 7, JULY 2008 Effective Radii of On-Chip Decoupling Capacitors
• Predictions, Challenges, and Opportunities in CMOS Compatible On-Chip Optical Interconnect
• Electrical Characteristics of Multi-Layer Power Distribution Grids Andrey V. Mezhiba and Eby G. Friedman
• On-Chip Power Distribution Grids with Multiple Supply Voltages for High Performance Integrated Circuits
• Maximum Effective Distance of On-Chip Decoupling Capacitors in Power Distribution Grids
• Inductive Characteristics of Power Distribution Grids in High Speed Integrated Circuits
• BUFFER SIZING FOR DELAY UNCERTAINTY INDUCED BY PROCESS VARIATIONS Dimitrios Velenis and Ramyashree Sundaresha
• Journal of Circuits, Systems, and Computers, Vol. 11, No. 3 (2002) 305321 c World Scientific Publishing Company
• Nanoscale On-Chip Decoupling Capacitors Mikhail Popovich
• An Intra-Chip Free-Space Optical Interconnect Jing Xue, Alok Garg, Berkehan Ciftcioglu, Jianyun Hu, Shang Wang
• Line Width Optimization for Interdigitated Power/Ground Networks
• A HIGH-SPEED CMOS OP-AMP DESIGN TECHNIQUE USING NEGATIVE MILLER CAPACITANCE
• Journal of Circuits, Systems, and Computers Vol. 18, No. 7 (2009) 12631285
• Sensitivity of Interconnect Delay to On-Chip Inductance Yehea I. Ismail and Eby G. Friedman
• Design Methodology for Global Resonant H-Tree Clock Distribution Networks
• Mutual Inductance Modeling for Multiple RLC Interconnects with Application to Shield Insertion Junmou Zhang and Eby G. Friedman
• IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS, VOL. 9, NO. 6, DECEMBER 2001 963 Exploiting the On-Chip Inductance in High-Speed
• 908 IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS, VOL. 16, NO. 7, JULY 2008 On-Chip Power Distribution Grids With
• Transformations of Signed-Binary Number Representations for Efficient VLSI Arithmetic
• IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS, VOL. 10, NO. 4, AUGUST 2002 487 Simultaneous Switching Noise in On-Chip
• 24 IEEE CIRCUITS AND SYSTEMS MAGAZINE FIRST QUARTER 2003 Yehea I. Ismail and Eby G. Friedman
• A 0.8 Volt High Performance OTA Using Bulk-Driven MOSFETs for Low Power Mixed-Signal SOCs
• IEEE TRANSACTIONS ON COMPUTER-AIDED DESIGN OF INTEGRATED CIRCUITS AND SYSTEMS, VOL. 16, NO. 1, JANUARY 1997 105 Incorporating Interconnect, Register, and Clock
• Department of Electrical and Computer Engineering University of Wisconsin-Madison
• Methodology for Multi-Layer Interdigitated Power and Ground Network Design
• An Intra-Chip Free-Space Optical Interconnect Jing Xue, Alok Garg, Berkehan Ciftcioglu, Shang Wang, Jianyun Hu, Ioannis Savidis,
• IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS, VOL. 17, NO. 10, OCTOBER 2009 1405 Methodology for Efficient Substrate Noise Analysis
• Abstract Four different dynamic circuit techniques are proposed in this paper for lowering the active mode power consumption, increasing the speed, enhancing the noise immunity, and reducing the subthreshold leakage energy of domino logic circuits. A var
• A Semi-analytical Simulation model for Capacitor Based E-O Modulators
• Clock Tree Layout Design for Reduced Delay Uncertainty Dimitrios Velenis
• Figures of Merit to Characterize the Importance of On-Chip Inductance
• 378 INTEGRATED CIRCUIT SIGNAL DELAY INTEGRATED CIRCUIT SIGNAL DELAY
• CHOICE OF THE OPTIMUM TIMING SCHEME FOR RSFQ DIGITAL Kris Gaj, Eby G. Friedman, and Marc J. Feldman
• 2010 IEEE 26-th Convention of Electrical and Electronics Engineers in Israel 978-1-4244-8682-3/10/$26.00 2010 IEEE
• Decoupling Technique and Crosstalk Analysis for Coupled RLC Interconnects Junmou Zhang and Eby G. Friedman
• 240 IEEEJOURNALOFSOLID-STATECIRCUITSVOL.SC-21,NO.2, APRIL1986 Design and Analysis of a Hierarchical Clock
• Analog Integrated Circuits and Signal Processing, 31, 209224, 2002 C 2002 Kluwer Academic Publishers. Manufactured in The Netherlands.
• Interconnect Delay Minimization through Interlayer Via Placement in 3-D ICs
• Electrical and Optical On-Chip Interconnects in Scaled Microprocessors Guoqing Chen, Hui Chen, Mikhail Haurylau, Nicholas Nelson, David Albonesi, Philippe M. Fauchet, and Eby G. Friedman
• Analog Integrated Circuits and Signal Processing, 35, 207214, 2003 C 2003 Kluwer Academic Publishers. Manufactured in The Netherlands.
• An Area Efficient Fully Monolithic Hybrid Voltage Regulator Selcuk Kose and Eby G. Friedman
• Minimizing Sensitivity to Delay Variations in High-Performance Synchronous Circuits
• Input Port Reduction for Efficient Substrate Extraction in Large Scale IC's
• Inductance Effects in RLC Trees Yehea I. Ismail, Eby G. Friedman, and Jose L. Neves
• Efficient Implementation of a Complex 1 Multiplier Boris D. Andreev, Eby G. Friedman, and Edward L. Titlebaum
• 474 IEEE JOURNAL OF SOLID-STATE CIRCUITS, VOL. 41, NO. 2, FEBRUARY 2006 On-Chip Test Circuit for Measuring Substrate and
• INTEGRATION, the VLSI journal 38 (2004) 205225 Optimum wire sizing of RLC interconnect with repeaters
• Equivalent Elmore Delay for RLC Trees Yehea I. Ismail, Eby G. Friedman, and Jose L. Neves1
• Interconnect Coupling Noise in CMOS VLSI Circuits Kevin T. Tang and Eby G. Friedman
• Methodology to Achieve Higher Tolerance to Delay Variations in Synchronous Circuits
• Substrate Noise Reduction Based On Noise Aware Cell Design
• Methodology for Placing Localized Guard Rings to Reduce Substrate Noise in Mixed-Signal Circuits
• 386 IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS, VOL. 12, NO. 4, APRIL 2004 Scaling Trends of On-Chip Power Distribution Noise
• Pseudo-Random Clocking to Enhance Signal Integrity Selcuk Kose, Emre Salman, Zeljko Ignjatovic, and Eby G. Friedman
• Interconnect-Based Design Methodologies for
• 774 IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS, VOL. 19, NO. 5, MAY 2011 Multi-Layer Interdigitated Power
• Estimation of On-Chip Simultaneous Switching Noise on Signal Delay in Synchronous CMOS Integrated Circuits
• Timing of Large RSFQ Digital Circuits Kris Gaj, Eby G. Friedman, and Marc J.Feldman
• Analog Integrated Circuits and Signal Processing, 14, 2939 (1997) c 1997 Kluwer Academic Publishers, Boston. Manufactured in The Netherlands.
• A Universal CMOS Voltage Interface Circuit Radu M. Secareanu, Eby G. Friedman, Juan Becerra, and Scott Warner
• Analog Integrated Circuits and Signal Processing, 31, 249259, 2002 C 2002 Kluwer Academic Publishers. Manufactured in The Netherlands.
• IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS--I: FUNDAMENTAL THEORY AND APPLICATIONS, VOL. 47, NO. 10, OCTOBER 2000 1515 Briefs___________________________________________________________________________________________
• Noise Coupling in Multi-Voltage Power Distribution Systems with Decoupling Capacitors
• Repeater Insertion in RLC Lines for Minimum Propagation Delay Yehea I. Ismail and Eby G. Friedman
• Delay and Power Expressions for a CMOS Inverter Driving a Resistive-Capacitive Load
• Clock Distribution Networks for 3-D Integrated Circuits Vasilis F. Pavlidis, Ioannis Savidis, and Eby G. Friedman
• A Fourier Series-Based RLC Interconnect Model for Periodic Signals Guoqing Chen and Eby G. Friedman
• IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS, VOL. 19, NO. 6, JUNE 2011 1075 A Distributed Filter Within a Switching Converter for
• Clock Distribution Models of 3-D Integrated Systems Ioannis Savidis, Vasilis Pavlidis, and Eby G. Friedman
• Distributed Power Network Co-Design with On-Chip Power Supplies and Decoupling Capacitors
• Fast Algorithms for IR Voltage Drop Analysis Exploiting Locality
• IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS, VOL. 19, NO. 11, NOVEMBER 2011 2095 Linear and Switch-Mode Conversion in 3-D Circuits
• 2256 IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS, VOL. 19, NO. 12, DECEMBER 2011 Clock Distribution Networks in
• IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS--II: EXPRESS BRIEFS, VOL. 58, NO. 11, NOVEMBER 2011 739 Effective Resistance of a Two Layer Mesh
• 1458 IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS, VOL. 19, NO. 8, AUGUST 2011 Shielding Methodologies in the Presence of
• 3-D integrated heterogeneous intra-chip free-space optical interconnect
• Utilizing interdependent timing constraints to enhance robustness in synchronous circuits
• World abstracts on microelectronicsand reliability 557 optimizing clock trees, especially for high-speed
• Efficient algorithms for fast IR drop analysis exploiting locality Selc-uk Kose n
• Multi-aggressor capacitive and inductive coupling noise modeling and mitigation