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- ILP-based Scheduling for Asynchronous Circuits in Bundled-Data Implementation
- Verification of Timed Circuits with Failure Directed Abstractions
- LEARNING GENETIC REGULATORY NETWORK CONNECTIVITY FROM TIME SERIES DATA
- Speed-Independent PRs Simplified Timed PRs !"# !" $ !"%'&)(01
- Direct Synthesis of Timed Asynchronous Circuits Sung Tae Jung and Chris J. Myers
- PROTOCOL SELECTION, IMPLEMENTATION, AND ANALYSIS FOR ASYNCHRONOUS CIRCUITS
- Abstracted Stochastic Analysis of Type 1 Pili Expression in E. coli
- Automatic Verification of Timed Circuits Tomas G. Rokicki
- The Design of a Genetic Muller C-Element Nam-Phuong D. Nguyen, Hiroyuki Kuwahara, Chris J. Myers, James P. Keener
- FAC 2005 Preliminary Version The Case for Analog Circuit Verification
- Analog/Mixed-Signal Circuit Verification Using Models Generated from Simulation Traces
- Framework of Timed Trace Theoretic Verification Revisited Bin Zhou Tomohiro Yoneda
- A Comparison of Timed State Space Analysis Methods Scott R. Little
- Electronic Notes in Theoretical Computer Science 65 No. 6 (2002) URL: http://www.elsevier.nl/locate/entcs/volume65.html 22 pages
- Learning Genetic Regulatory Network Connectivity from Time Series Data
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- High Level Synthesis of Timed Asynchronous Circuits Tomohiro Yoneda
- IEEE TRANSACTIONS ON COMPUTER-AIDED DESIGN OF INTEGRATED CIRCUITS AND SYSTEMS, VOL. 20, NO. 1, JANUARY 2001 129 Timed Circuit Verification Using TEL Structures
- A NEW VERIFICATION METHOD FOR EMBEDDED SYSTEMS
- MODEL ABSTRACTION AND TEMPORAL BEHAVIOR ANALYSIS OF GENETIC
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- TECHNOLOGY MAPPING OF TIMED ASYNCHRONOUS CIRCUITS
- CORRECTNESS AND REDUCTION IN TIMED CIRCUIT ANALYSIS
- DESIGN AND ANALYSIS OF GENETIC CIRCUITS Nam-phuong D. Nguyen
- ANALYSIS AND CHARACTERIZATION OF A LOCALLY-CLOCKED MODULE
- Automated Abstraction of Labeled Petri Nets Kevin Jones
- MODELING AND VISUALIZATION OF SYNTHETIC GENETIC CIRCUITS
- Efficient Verification of Hazard-Freedom in Gate-Level Timed Asynchronous Circuits
- Automated Abstraction Methodology for Genetic Regulatory Networks
- Modular Verification of Timed Circuits Using Automatic Abstraction
- An Asynchronous Instruction Length Decoder Ken Stevens1, Shai Rotem1, Ran Ginosar1 2, Peter Beerel3, Chris Myers4,
- Copy provided by USPTO from the CSIR Image Database on 08-16-2000 Copy provided by USPTO from the CSIR Image Database on 08-16-2000
- A New Verification Method For Embedded Systems Robert A. Thacker, Chris J. Myers and Kevin Jones
- Synthesis of Genetic Circuits from Graphical Specifications Nam-Phuong D. Nguyen, Nathan Barker, Hiroyuki Kuwahara, Curtis Madsen, Chris J. Myers
- Production-Passage-Time Approximation: A New Approximation Method to Accelerate the
- Symbolic Model Checking of Analog/Mixed-Signal Circuits David Walter, Scott Little, Nicholas Seegmiller, Chris J. Myers Tomohiro Yoneda
- Partial Order Reduction for Detecting Safety and Timing Failures of Timed Circuits
- Synthesis of Speed Independent Circuits Based on Decomposition Tomohiro Yoneda
- EFFICIENT VERIFICATION OF HAZARD-FREEDOM IN GATE-LEVEL TIMED ASYNCHRONOUS CIRCUITS
- Automatic Derivation of Timing Constraints by Failure Analysis
- Synchronous Interlocked Pipelines Hans M. Jacobson Prabhakar N. Kudva Pradip Bose Peter W. Cook Stanley E. Schuster
- "!#%$&'($0)21436587@9ABBDCFE@"!AC G"H#IQPSR $TU R !VE@ W GYX
- STOCHASTIC CYCLE PERIOD ANALYSIS IN TIMED CIRCUITS Eric G. Mercer and Chris J. Myers
- Verification of Delayed-Reset Domino Circuits Using ATACS Wendy Belluomini
- Verification of Delayed-Reset Domino Circuits Using ATACS Wendy Belluomini
- Timed Circuit Synthesis Using Implicit Methods Robert A. Thacker Wendy Belluomini Chris J. Myers
- Verification of Timed Systems Using POSETs Wendy Belluomini
- Timed Event/Level Structures Wendy Belluomini Chris J. Myers
- Synthesis of Timed Circuits using BDDs Robert A. Thacker Chris J. Myers
- Efficient Timing Analysis Algorithms for Timed State Space Exploration Wendy Belluomini
- AUTOMATIC EXTRACTION OF BEHAVIORAL MODELS FROM SIMULATIONS OF
- Improved POSET Timing Analysis in Timed Petri Nets Eric G Mercer
- Bounded Model Checking of Analog and Mixed-Signal Circuits Using an SMT Solver
- Hazard Checking of Timed Asynchronous Circuits Revisited Frederic Beal
- CELL LIBRARY FOR AUTOMATIC SYNTHESIS OF ANALOG ERROR CONTROL Jie Dai, Chris J. Winstead, Chris J. Myers, Reid R. Harrison, Christian Schlegel
- Direct Synthesis of Timed Asynchronous Circuits Sung Tae Jung and Chris J. Myers
- RAPPID: An Asynchronous Instruction Length Decoder Shai Rotem1
- Abstract Modeling and Simulation Aided Verification of Analog/Mixed-Signal Circuits
- Copy provided by USPTO from the CSIR Image Database on 08-16-2000 Copy provided by USPTO from the CSIR Image Database on 08-16-2000
- Copy provided by USPTO from the CSIR Image Database on 08-16-2000 Copy provided by USPTO from the CSIR Image Database on 08-16-2000
- Verifying Synchronization Strategies Chris J. Myers1
- EFFICIENT MODELING AND VERIFICATION OF ANALOG/MIXED-SIGNAL CIRCUITS USING
- Efficient Exact Two-Level Hazard-Free Logic Minimization Chris Myers
- ICMP0220U : 532; 533; 533.9:530.182; 536.75; 536-12.01.
- Level Oriented Formal Model for Asynchronous Circuit Verification and its Efficient Analysis Method
- IEEE TRANSACTIONS ON COMPUTER-AIDED DESIGN OF INTEGRATED CIRCUITS AND SYSTEMS, VOL. 26, NO. 7, JULY 2007 1 Synthesis of Timed Circuits Based on Decomposition
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- A Scheduling Method for Asynchronous Bundled-Data Implementations Based on The Completion of Data Operations
- Verification of Analog and Mixed-Signal Circuits Using Timed Hybrid Petri Nets
- DESIGN METHODOLOGY FOR ANALOG VLSI IMPLEMENTATIONS OF ERROR CONTROL
- Verification of Analog/Mixed-Signal Circuits Using Labeled Hybrid Petri Nets
