Markatos, Evangelos P. - Department of Computer Science, University of Crete

• Detecting Targeted Attacks Using Shadow Honeypots K. G. Anagnostakis
• Security and Privacy Architectures for Biomedical Cloud Computing Vasiliki Danilatou and Sotiris Ioannidis
• Network Monitoring Session Description Augusto Ciuffoletti
• Design and Implementation of a PerFlow Queue Manager for an ATM Switch using FPGA technology
• Architecture of a Network Monitoring Element Augusto Ciuffoletti
• Using reference counters in Update Based Coherent Memory Evangelos P. Markatos and Catherine E. Chronaki
• Scheduling in Non-Blocking Buffered Three-Stage Switching Fabrics
• Harnessing the power of P2P systems for fast attack signature validation Spiros Antonatos, Vu Quang Hieu
• 11-04-13 17:28Exercises 8: Input Q'ing, VOQ Xbar Scheduling, and Simulation (U.Crete, CS-534) Page 1 of 3http://www.csd.uoc.gr/~hy534/11a/ex08_sim.html
• On Caching Search Engine Query Results Evangelos P. Markatos
• Weighted RoundRobin Cell Multiplexing in a GeneralPurpose ATM Switch Chip
• 11-03-25 11:29Lab 7: RC, RLC under Sinusoidal Sources (U.Crete, CS-121) Page 1 of 3http://www.csd.uoc.gr/~hy121/11a/lab07_AC2.html
• Exercises 5: Linked-List Queue Management (U.Crete, CS-534) http://archvlsi.ics.forth.gr/~kateveni/534/08a/ex05_llq.html CS-534: Packet Switch Architecture
• Exercises 12: Output Scheduling for QoS (U.Crete, CS-534) http://archvlsi.ics.forth.gr/~kateveni/534/08a/ex12_sched.html CS-534: Packet Switch Architecture
• Exercises 11: Flow Control (U.Crete, CS-534) http://archvlsi.ics.forth.gr/~kateveni/534/08a/ex11_flowCtrl.html CS-534: Packet Switch Architecture
• Predicting Archival Life of Removable Hard Disk Drives Paul Williams; ProStor Systems, Inc.; Boulder, CO., USA / David S. H. Rosenthal; Stanford University Libraries; Stanford, CA., USA /
• Experiences from Debugging a PCIX-based RDMA-capable NIC Manolis Marazakis, Vassilis Papaefstathiou, Giorgos Kalokairinos, and Angelos Bilas
• 11-03-01 20:18Exercises 3: Memory Access Rate, Packet Segmentation (U.Crete, CS-534) Page 1 of 3http://www.csd.uoc.gr/~hy534/11a/ex03_memRate.html
• Exercises 7: Input Queueing and Crossbar Scheduling (U.Crete, CS-534) http://archvlsi.ics.forth.gr/~kateveni/534/08a/ex07_inQ.html 1 of 3 4/16/2008 1:53 AM
• STRIDE: POLYMORPHIC SLED DETECTION THROUGH INSTRUCTION SEQUENCE
• Combining Static and Dynamic Analysis for the Detection of Malicious Documents
• Evaluation of Compression of Remote Network Monitoring Data Streams
• An FPGA-based Prototyping Platform for Research in High-Speed Interprocessor Communication
• 10-10-03 11:28Lab 3: Comb. Logic, Gates, IC's (U.Crete, CS-120) Page 1 of 10http://www.csd.uoc.gr/~hy120/10f/lab03_combIC.html
• An E cient Processor-Network Interface for Local Area Multiprocessors
• Exercise 12: Completing the Processor Instructions (U.Crete, CS-225) http://www.csd.uoc.gr/~hy225/09a/ex12_otherI.html 29 2009, 23:59 ( 11)
• 3.1 TDM, Time Switching, Cut-Through 3.2 Wide Memories for High Thruput, Segm'tn Ovrhd
• 10-09-16 18:23Course Description (U.Crete, CS-120) Page 1 of 4http://www.csd.uoc.gr/~hy120/10f/intro.html
• 2.1 Links 1 2.1 Links, Thruput/Buffering, Multi-Access Ovrhds
• Scheduling in Switches with Small Internal Buffers Nikos Chrysos and Manolis Katevenis
• Packet Mode Scheduling in Buffered Crossbar (CICQ) Switches
• Asynchronous Operation of Bufferless Crossbars Georgios Passas 1 and Manolis Katevenis 1
• FORTH-ICS / TR-094 August 1993 Locality-Based Scheduling
• Exercises 10: Switching Fabric Topologies (U.Crete, CS-534) http://archvlsi.ics.forth.gr/~kateveni/534/08a/ex10_fabrics.html 1 of 2 5/12/2008 2:37 AM
• Exercises 8: Queueing Architecture SRAM Cost (U.Crete, CS-534) http://archvlsi.ics.forth.gr/~kateveni/534/08a/ex08_qArch.html CS-534: Packet Switch Architecture
• Exercises 9: TST & Clos Ckt Sw. Scheduling (U.Crete, CS-534) http://archvlsi.ics.forth.gr/~kateveni/534/08a/ex09_tst_sch.html CS-534: Packet Switch Architecture
• Exercises 6: Multi-Packet Blocks, Multicast Queues (U.Crete, CS-534) http://archvlsi.ics.forth.gr/~kateveni/534/08a/ex06_advq.html CS-534: Packet Switch Architecture
• Tracing a large-scale Peer to Peer System: an hour in the life of Gnutella
• 1. Basic Concepts and Queueing Architectures 2. High-Throughput Multi-Queue Memories
• we.b: The web of short URLs Demetris Antoniades
• EVALUATION OF 3D RECONSTRCUTION USING MULTIVIEW BACKPROJECTION K. Mueller1
• Verilog 10-13 .
• Improving the Performance of Passive Network Monitoring Applications using Locality Buffering
• FORTH/ICS/TR/030 July 1993 TRACE-DRIVEN SIMULATION OF DATA-ALIGNMENT
• Experimental ATM Network Interface Performance Apostolos Dollas Kyprianos Papadimitriou Constantinos Mathioudakis
• 11-05-10 21:33Lab 11: Schmitt Trigger (U.Crete, CS-121) Page 1 of 2http://www.csd.uoc.gr/~hy121/11a/lab11_schmTr.html
• Abstract-The advance of regional healthcare networks has cre-ated increasing demand for telemedicine services tailored to
• 09-09-21 00:27A Welcome Note (U.Crete, CS-120) Page 1 of 10http://www.csd.uoc.gr/~hy120/09f/welcome.html
• 09-10-07 03:38Lab 3: Comb. Logic, Gates, IC's (U.Crete, CS-120) Page 1 of 10http://www.csd.uoc.gr/~hy120/09f/lab03_combIC.html
• 09-10-22 20:27Lab 6: Signed Add/Subtract, FF (U.Crete, CS-120) Page 1 of 8http://www.csd.uoc.gr/~hy120/09f/lab06_sub.html
• 09-11-06 19:39Lab 8: Counter, Edge-Triggering (U.Crete, CS-120) Page 1 of 8http://www.csd.uoc.gr/~hy120/09f/lab08_edge.html
• 09-11-13 20:16Lab 9: Tri-State Buses, SRAM (U.Crete, CS-120) Page 1 of 7http://www.csd.uoc.gr/~hy120/09f/lab09_3st.html
• 09-11-27 00:17Lab 11: Datapath of a simple Processor (U.Crete, CS-120) Page 1 of 11http://www.csd.uoc.gr/~hy120/09f/lab11_dpath.html
• 09-12-04 21:17Lab 12: Branches and Pointers (U.Crete, CS-120) Page 1 of 10http://www.csd.uoc.gr/~hy120/09f/lab12_br_ptr.html
• 3.1 TDM, Time Switching, Cut-Through 3.2 Wide Memories for High Thruput, Segm'tn Ovrhd
• 10-12-08 10:51Lab 11: Datapath of a simple Processor (U.Crete, CS-120) Page 1 of 11http://www.csd.uoc.gr/~hy120/10f/lab11_dpath.html
• 4 2009, ( 5.2)( 3.2) ( , , , .5)
• CS-534 -Copyright University of Crete 1 6.3 Buffer Space vesrus Number of Flows
• UNCORRECTED FUTURE: 1534 + Model pp. 115 (col. fig: NIL)
• 5. Switching Fabrics 1 3. Output Queueing Architectures
• 10-05-06 00:13Lab 10: MOS FET's and the CMOS Inverter (U.Crete, CS-121) Page 1 of 2http://www.csd.uoc.gr/~hy121/10a/lab10_mosfet.html
• On Using Network Memory to Improve the Performance of Transaction-Based Systems
• http://archvlsi.ics.forth.gr/~kateveni/534/ 6.3 Buffer Space vs. Number of Flows 1
• Alice, what did you do last time? Fighting Phishing Using Past Activity Tests
• Exclusion-based Signature Matching for Intrusion Detection Evangelos P. Markatos, Spyros Antonatos, Michalis Polychronakis, Kostas G. Anagnostakis
• 3.1 TDM, Time Switching, Cut-Through 3.2 Wide Memories for High Thruput, Segm'tn Ovrhd
• Puppetnets: Misusing Web Browsers as a Distributed Attack Infrastructure
• LOBSTER: A European Platform for Passive Network Traffic Monitoring
• 10-09-28 22:23Lab 2: Relays, Muxes, Feedback (U.Crete, CS-120) Page 1 of 10http://www.csd.uoc.gr/~hy120/10f/lab02_relays.html
• PROTOTYPE IMPLEMENTATION OF A DEMAND DRIVEN NETWORK MONITORING ARCHITECTURE
• 4.1 Intro: Time-Space Sw.; Input Q'ing w/o VOQ's 4.2 Input Queueing with VOQ's: Crossbar Scheduling
• A survey of Evasiveness: Lower Bounds on the DecisionTree Complexity of
• 11-02-14 00:19Course Description (U.Crete, CS-534) Page 1 of 2file:///Users/kateveni/public_html/534/11a/intro.html
• GAS: Overloading a File Sharing Network as an Anonymizing System
• Network-Level Polymorphic Shellcode Detection Using Emulation
• 4.1 Intro: Time-Space Sw.; Input Q'ing w/o VOQ's 4.2 Input Queueing with VOQ's: Crossbar Scheduling
• On Using Network RAM as a non-volatile Bu er Dionisios Pnevmatikatos Evangelos P. Markatos
• 16 2009, 23:59 ( 3.1) ( . 2.1) [Up: Table of Contents]
• 11-03-22 23:32Exercises 6: Multi-Packet Blocks, Multicast Queues (U.Crete, CS-534) Page 1 of 2http://www.csd.uoc.gr/~hy534/11a/ex06_advq.html
• Cnet Service Architecture Paradigm Xenophon Zabulis1,2
• PASSIVEEND-TO-ENDPACKETLOSSESTIMATION FOR GRID TRAFFIC MONITORING
• 3.3, 3.4: Multiple & Multicast Queues 1 3.1 TDM, Time Switching, Cut-Through
• Lightweight Transactions on Networks of Workstations Athanasios E. Papathanasiou Evangelos P. Markatos
• FORTHICS / TR114 January 1994 An Arithmetic Entropy Codec VLSI chip
• 10-10-15 11:32Lab 5: Binary Numbers, Addition (U.Crete, CS-120) Page 1 of 8http://www.csd.uoc.gr/~hy120/10f/lab05_add.html
• Speeding up TCP/IP: Faster Processors are not Enough Evangelos P. Markatos
• 3.1 Time Switching, Cut-Through 1 3.1 TDM, Time Switching, Cut-Through
• Isolating JavaScript in Dynamic Code Environments Antonis Krithinakis Elias Athanasopoulos Evangelos P. Markatos
• 4.2 IQ w.VOQs: Crossbar Sched'ing 1 4.1 Intro: Time-Space Sw.; Input Q'ing w/o VOQ's
• http://archvlsi.ics.forth.gr/~kateveni/534/ 6.1 Credit-Based Flow Control (Backpressure) 1
• Exercise 10: Processor Datapath (U.Crete, CS-225) http://www.csd.uoc.gr/~hy225/09a/ex10_datapath.html Datapath
• Scheduling in Non-Blocking Buffered Three-Stage Switching Fabrics
• Simulator of Patient Traffic in a Cardiology Department for Testing the Integration of an ECG Management System with an Existing Clinical Database
• Interconnectivity of Cardiology Patient Databases using Internet Technology PJ Lees, CE Chronaki, F Chiarugi, E Tsiknakis, SC Orphanoudakis
• Integrated Teleconsultation Services in Cardiology C Chronaki, S Kostomanolakis, P Lelis, PJ Lees, F Chiarugi, M Tsiknakis, SC Orphanoudakis
• This leaflet was co-funded (70%) by the European Union and (30%) by the Hellenic Republic, through the Measure 4.4.5: "HERMES/Open
• Curriculum Vitae for Xenophon Zabulis Date of birth: 27 October 1973
• University of Crete Department of Computer Science
• Use of autonomous software entities in the resource management of an emergency prehospital medical system
• Real-time Terascale Implementation of Tele-immersion Nikhil Kelshikar1
• Hindawi Publishing Corporation EURASIP Journal on Advances in Signal Processing
• This article was published in an Elsevier journal. The attached copy is furnished to the author for non-commercial research and
• 30th Annual International IEEE EMBS Conference Vancouver, British Columbia,Canada,August 20-24,2008
• An efficient and memory-conserving implementation of multi-view stereo for wide-area reconstruction
• REGION-BASED DENSE DEPTH EXTRACTION FROM MULTI-VIEW VIDEO Cevahir i la1
• ECIS 2007 Abstract TXXX A composite image analysis system for the determination of size distribution in densely
• MODULATING THE SIZE OF BACKPROJECTION SURFACE PATCHES, IN VOLUMETRIC STEREO, FOR INCREASING RECONSTRUCTION ACCURACY AND ROBUSTNESS
• SEGMENT-BASED STEREO-MATCHING VIA PLANE AND ANGLE SWEEPING Cevahir ila1
• Efficient, Precise, and Accurate Utilization of the Uniqueness Constraint in Multi-View Stereo
• INCREASING THE ACCURACY OF THE SPACE-SWEEPING APPROACH TO STEREO RECONSTRUCTION, USING SPHERICAL BACKPROJECTION SURFACES.
• EFFICIENT, PRECISE, AND ACCURATE UTILIZATION OF THE UNIQUENESS CONSTRAINT IN SELF-CALIBRATED STEREO
• Volumetric multi-camera scene acquisition with partially metric calibration for wide-area tele-immersion
• 11/11/2006 02:04 PMJournal of Vision -The starry night texture and its use to isolate depth cues, by Zabulis & Backus Page 1 of 2http://www.journalofvision.org/2/7/234/
• Shape Similarity by Piecewise Linear Alignment Jon Sporring, Xenophon Zabulis, Panos E. Trahanias, and Stelios C. Orphanoudakis
• Introduction ICSICS--FORTHFORTH UOCUOC
• Institute for Research in Cognitive Science IRCS Technical Reports Series
• Scale Summarized and Focused Browsing of Primitive Visual Content
• (IJCNS) International Journal of Computer and Network Security, Vol. 2, No. 9, September 2010
• Decentralized Access Control in Distributed File Systems STEFAN MILTCHEV and JONATHAN M. SMITH
• DIVIDE ET IMPERA: PARTITIONINGUNSTRUCTUREDPEER-TO-PEER
• An Active Splitter Architecture for Intrusion Detection and Prevention
• Using Processor A nity in Loop Scheduling on Shared-Memory Multiprocessors
• CAPTCHuring Automated (Smart)Phone Attacks Iasonas Polakis, Georgios Kontaxis and Sotiris Ioannidis
• Outsourcing Malicious Infrastructure to the Cloud Georgios Kontaxis, Iasonas Polakis, Sotiris Ioannidis
• Dynamic Monitoring of Dark IP Address Space Iasonas Polakis, Georgios Kontaxis,
• GPU-Assisted Malware Giorgos Vasiliadis
• Using Social Networks to Harvest Email Addresses Iasonas Polakis
• Experiences and observations from the NoAH infrastructure Georgios Kontaxis, Iasonas Polakis, Spiros Antonatos and Evangelos P. Markatos
• RRDtrace: Long-term Raw Network Traffic Recording using Fixed-size Storage
• xJS: Practical XSS Prevention for Web Application Development Elias Athanasopoulos, Vasilis Pappas, Antonis Krithinakis, Spyros Ligouras, Evangelos P. Markatos
• Imbuing Unstructured P2P Systems with Non-intrusive Topology Awareness Harris Papadakis, Mema Roussopoulos, Paraskevi Fragopoulou1 and Evangelos P. Markatos
• Real-world Polymorphic Attack Detection Michalis Polychronakis,1
• Code-Injection Attacks in Browsers Supporting Policies Elias Athanasopoulos, Vasilis Pappas, and Evangelos P. Markatos
• Realistic Passive Packet Loss Measurement for High-Speed Networks
• WISDOM: Security-Aware Fibres Elias Athanasopoulos,
• Deep Packet Anonymization Michael Foukarakis, Demetres Antoniades, Michalis Polychronakis
• Real-world Polymorphic Attack Detection using Network-level Emulation
• Ghost turns Zombie: Exploring the Life Cycle of Web-based Malware
• Monitoring three National Research Networks for Eight Weeks: Observations and Implications
• When AppMon met Stager Nikos Nikiforakis, Demetres Antoniades, Evangelos P. Markatos, Sotiris Ioannidis
• Honey@home: A New Approach to Large-Scale Threat S. Antonatos, E. P. Markatos
• Flexible and High-Performance Anonymization of NetFlow Records using Anontool
• Emulation-based Detection of Non-self-contained Polymorphic Shellcode
• A FEEDBACK-BASED APPROACH TO REDUCE DUPLICATE MESSAGES IN UNSTRUCTURED
• ONTHEINTEGRATIONOFPASSIVEANDACTIVE NETWORK MONITORING IN GRID SYSTEMS
• On the Privacy Risks of Publishing Anonymized IP Network Traces
• TAO: Protecting Against Hitlist Worms Using Transparent Address Obfuscation
• Architecture of a Network Monitoring Element Augusto Ciuffoletti1
• Available bandwidth measurement as simple as running wget
• Defending against Hitlist Worms using Network Address Space Randomization
• Efficient Content-Based Detection of Zero-Day Worms P. Akritidis , K. Anagnostakis, E. P. Markatos
• DESIGN AND IMPLEMENTATION OF A HIGH-PERFORMANCE NETWORK
• PIRANHA: FAST AND MEMORY-EFFICIENT PATTERN MATCHING FOR INTRUSION
• SCAMPI -A Scaleable Monitoring Platform for the Internet Jan Coppens
• An Active Traffic Splitter Architecture for Intrusion Detection I. Charitakis , K. Anagnostakis
• Secondary Storage Management for Web Proxies Evangelos P. Markatos Manolis G.H. Katevenis
• Lightweight Transactions on Networks of Workstations Athanasios E. Papathanasiou Evangelos P. Markatosy
• Using Remote Memory to avoid Disk Thrashing: A Simulation Study
• Implementation of a Reliable Remote Memory Pager Evangelos P. Markatos and George Dramitinos
• Adding Flexibility to a Remote Memory Pager Evangelos P. Markatos George Dramitinos
• Defending against Hitlist Worms using Network Address Space Randomization K. G. Anagnostakis
• A Network-Processor-Based Traffic Splitter for Intrusion Detection
• Speeding up TCP/IP: Faster Processors are not Enough Evangelos P. Markatos
• A Cash-based Approach to Caching Web Documents Evangelos P. Markatos
• The Network RamDisk : Using Remote Memory on Heterogeneous NOWs
• Issues in the Design and Implementation of User-Level DMA Evangelos P. Markatos Manolis G.H. Katevenis
• User-Level DMA without Operating System Kernel Modi cation
• A Top-10 Approach to Prefetching on the Web Evangelos P. Markatos and Catherine E. Chronaki
• ArrayTracer: A Parallel Performance Analysis Tool Titos Saridakis (sarid@ics.forth.gr) Christos Nikolaou (nikolau@ics.forth.gr)
• Telegraphos: High-Performance Networking for Parallel Processing on Workstation Clusters
• Implementation and Evaluation of a Remote Memory Pager Evangelos P. Markatos George Dramitinos
• Towards Unified Mechanisms for Inter-Processor Communication
• ReplicateandMigrateObjectsintheRun5me notCacheLinesorPagesinHardware
• INTERPROCESSOR COMMUNICATION SEEN AS LOAD-STORE INSTRUCTION GENERALIZATION
• FPGA Implementation of a Configurable Cache/Scratchpad Memory with Virtualized
• A run-time Configurable Cache/Scratchpad Memory with Virtualized User-Level RDMA Capability
• A Run-time Configurable Cache/Scratchpad Memory with
• ! IEEE 2010 -Appears in IEEE Conference on Cluster Computing, September 2010, Heraklion, Crete, Greece 1 Low-latency Explicit Communication and Synchronization in
• Explicit Communication and Synchronization in SARC
• Asynchronous Operation of Bufferless Crossbars Georgios Passas1 and Manolis Katevenis1
• Scheduling in Switches with Small Internal Buffers Nikos Chrysos and Manolis Katevenis
• Scheduling in Switches with Small Internal Buffers: Extended Version
• Preventing Buffer-Credit Accumulations in Switches with Small, Shared Output Queues
• 10-09-16 16:21Lab 0: Breadboard, LED, Switch Introduction (U.Crete, CS-120) Page 1 of 6http://www.csd.uoc.gr/~hy120/10f/lab00_switches.html
• 10-09-23 23:27Lab 1: Logic with Switches (U.Crete, CS-120) Page 1 of 10http://www.csd.uoc.gr/~hy120/10f/lab01_swLogic.html
• 10-10-25 11:09Lab 6: Signed Add/Subtract, FF (U.Crete, CS-120) Page 1 of 8http://www.csd.uoc.gr/~hy120/10f/lab06_sub.html
• 10-11-01 12:24Lab 7: Latches & Clocks (U.Crete, CS-120) Page 1 of 6http://www.csd.uoc.gr/~hy120/10f/lab07_ff.html
• 10-11-05 11:18Lab 8: Counter, Edge-Triggering (U.Crete, CS-120) Page 1 of 8http://www.csd.uoc.gr/~hy120/10f/lab08_edge.html
• 10-11-29 07:19Lab 10: FSM (U.Crete, CS-120) Page 1 of 8http://www.csd.uoc.gr/~hy120/10f/lab10_fsm.html
• UNIVERSITY OF CRETE COMPUTER SCIENCE DEPARTMENT
• 10-10-04 02:53Extra 2: Delay Measurements, Feedback, Arbitration (U.Crete, CS-120) Page 1 of 3http://www.csd.uoc.gr/~hy120/10f/extra02_feedback.html
• 11-02-13 01:27Course Description (U.Crete, CS-121) Page 1 of 4http://www.csd.uoc.gr/~hy121/11a/intro.html
• 11-02-13 01:35Lab 1: Basic Equipment and Resistors (U.Crete, CS-121) Page 1 of 4http://www.csd.uoc.gr/~hy121/11a/lab01_intro.html
• 11-03-23 03:12Lab 6: RL under Sinusoidal Sources (U.Crete, CS-121) Page 1 of 3http://www.csd.uoc.gr/~hy121/11a/lab06_AC1.html
• 11-05-17 20:19Lab 12: Transmission Lines (U.Crete, CS-121) Page 1 of 2http://www.csd.uoc.gr/~hy121/11a/lab12_xmLines.html
• The Hardware Architect's Perspective on High-Speed Networking and Interconnects
• 1. Basic Concepts and Q'ing Arch. 1 The Hardware Architect's Perspective
• 11-02-15 20:26Exercises 1: Internal Blocking, Q'ing Arch. Throughput (U.Crete, CS-534) Page 1 of 2file:///Users/kateveni/public_html/534/11a/ex01_intro.html
• 2.1 Links, Thruput/Buffering, Multi-Access Ovrhds 2.2 Memories: On-chip / Off-chip SRAM, DRAM
• 2.2 RAM Technologies 1 2.1 Links, Thruput/Buffering, Multi-Access Ovrhds
• 2.A Elastic Buffers 1 2.1 Links, Thruput/Buffering, Multi-Access Ovrhds
• 3.1 TDM, Time Switching, Cut-Through 3.2 Wide Memories for High Thruput, Segm'tn Ovrhd
• 11-03-07 14:54Exercises 4: Switch Generations, Cut-through (U.Crete, CS-534) Page 1 of 1http://www.csd.uoc.gr/~hy534/11a/ex04_swGen_cutThr.html
• 11-03-15 18:53Exercises 5: Linked-List Queue Management (U.Crete, CS-534) Page 1 of 2http://www.csd.uoc.gr/~hy534/11a/ex05_llq.html
• 3.5 Output Queueing Family 1 3.1 TDM, Time Switching, Cut-Through
• 4.1 Introduction to Input Queueing 1 4.1 Intro: Time-Space Sw.; Input Q'ing w/o VOQ's
• 4.3 Adv.Topics in Crossbar Sched'ing 1 4.1 Intro: Time-Space Sw.; Input Q'ing w/o VOQ's
• 4.4 CIOQ, 4.5 CICQ 1 4.1 Intro: Time-Space Sw.; Input Q'ing w/o VOQ's
• 11-04-04 12:20Exercises 7: Queueing Architecture SRAM Cost (U.Crete, CS-534) Page 1 of 3http://www.csd.uoc.gr/~hy534/11a/ex07_qArch.html
• 3. Output Queueing Architectures 4. input Queueing Architectures
• 11-05-10 22:29Exercises 9: TST & Clos Ckt Sw. Scheduling (U.Crete, CS-534) Page 1 of 4http://www.csd.uoc.gr/~hy534/11a/ex09_tst_sch.html
• 11-05-12 19:29Exercises 10: Switching Fabric Topologies (U.Crete, CS-534) Page 1 of 2http://www.csd.uoc.gr/~hy534/11a/ex10_fabrics.html
• http://archvlsi.ics.forth.gr/~kateveni/534/ 6.2 Per-Flow Queueing & Flow Control 1
• http://archvlsi.ics.forth.gr/~kateveni/534/ 7.1 output Scheduling for QoS 1
• 11-05-26 20:43Exercises 12: Output Scheduling for QoS (U.Crete, CS-534) Page 1 of 4http://www.csd.uoc.gr/~hy534/11a/ex12_sched.html
• [printer version -PDF] [1. SPIM Introduction -Lectures & Exercises]
• 11 2009, 23:59 ( 2.2) ( .1.1) [Up: Table of Contents]
• 23 2009, 23:59 ( 4) ( 2.3) [Up: Table of Contents]
• 4 2009, ( 5.2)( 4.1) ( , , , .4)
• [Up -Table of Contents] [Prev -5. Compare and Branch]
• 16 2009, 23:59 ( 7) : , 21 2009, 11:15 -13:05
• Exercise 8: Verilog Introduction-1 (U.Crete, CS-225) www.csd.uoc.gr/~hy225/09a/ex08_verilog1.html Verilog
• Exercise 9: Verilog Introduction-2 (U.Crete, CS-225) www.csd.uoc.gr/~hy225/09a/ex09_verilog2.html Verilog
• Exercise 11: Basic Control FSM (U.Crete, CS-225) http://www.csd.uoc.gr/~hy225/09a/ex11_fsm.html 12 2009, 23:59 ( 10)
• Exercise 13: Exceptions and Final Debugging (U.Crete, CS-225) http://www.csd.uoc.gr/~hy225/09a/ex13_excep.html 9 2009, 23:59 ( 12)
• Exercise 15: Cache Memories (U.Crete, CS-225) http://www.csd.uoc.gr/~hy225/09a/ex15_caches.html 6 2009, ( 12)
• E U R O P E A N C U R R I C U L U M V I T A E
• XML Technology in support of Clinical Protocols for Teleconsultation
• C E R T I F I C A T EIQNet and DQS GmbH Deutsche Gesellschaft zur Zertifizierung von Managementsystemen
• 09-11-19 18:23Lab 10: FSM (U.Crete, CS-120) Page 1 of 8http://www.csd.uoc.gr/~hy120/09f/lab10_fsm.html
• On using Reliable Network RAM for Database Systems Athanasios E. Papathanasiou and Evangelos P. Markatos
• 3.2 Wide Memories, Segm'tn Ovrhd 1 3.1 TDM, Time Switching, Cut-Through
• 11-02-23 07:32Exercises 2: Rate, Throughput, Turn-Around Ovrhd (U.Crete, CS-534) Page 1 of 3http://www.csd.uoc.gr/~hy534/11a/ex02_thrup_turnAr.html
• An Empirical Study on the Security of Cross-Domain Policies in Rich Internet Applications
• Detecting Social Network Profile Cloning Georgios Kontaxis, Iasonas Polakis, Sotiris Ioannidis and Evangelos P. Markatos
• MOR: Monitoring and Measurements through the Onion Router
• On using Network Memory to Improve the Performance of Transaction-Based Systems
• 10-12-13 11:53Lab 12: Branches and Pointers (U.Crete, CS-120) Page 1 of 10http://www.csd.uoc.gr/~hy120/10f/lab12_br_ptr.html
• 4.1 Intro: Time-Space Sw.; Input Q'ing w/o VOQ's 4.2 Input Queueing with VOQ's: Crossbar Scheduling
• Topnet: A Network-Aware top(1) Antonis Theocharides, Demetres Antoniades, Michalis Polychronakis, Elias Athanasopoulos,
• 09-09-20 20:36Lab 0: Breadboard, LED, Switch Introduction (U.Crete, CS-120) Page 1 of 6http://www.csd.uoc.gr/~hy120/09f/lab00_switches.html
• A Greek (Privacy) Tragedy: The Introduction of Social Security Numbers in Greece
• Improving the Accuracy of Network Intrusion Detection Systems Under Load Using Selective Packet Discarding
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• 10-10-08 02:29Lab 4: Boolean Algebra, RAM (U.Crete, CS-120) Page 1 of 12http://www.csd.uoc.gr/~hy120/10f/lab04_karn_ram.html
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• 11-05-20 14:19Exercises 11: Flow Control (U.Crete, CS-534) Page 1 of 2http://www.csd.uoc.gr/~hy534/11a/ex11_flowCtrl.html
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• ATLAS I: A Single-chip ATM switch for NOWs Manolis G.H. Katevenis Panagiota Vatsolaki
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• Publications Book Chapters
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• Issues about the Integration of Passive and Active Monitoring for Grid Networks
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• 10-03-30 04:00Lab 6: RLC under Sinusoidal Sources (U.Crete, CS-121) Page 1 of 4http://www.csd.uoc.gr/~hy121/10a/lab06_AC.html
• 11-04-27 02:03Lab 10: Operational Amplifiers (U.Crete, CS-121) Page 1 of 3http://www.csd.uoc.gr/~hy121/11a/lab10_opAmp.html
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• 10-09-29 02:28Extra 1: Parity, Other Codes, Oscilloscopes (U.Crete, CS-120) Page 1 of 3http://www.csd.uoc.gr/~hy120/10f/extra01_swLogic.html
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• Pattern Recognition 38 (2005) 7593 www.elsevier.com/locate/patcog
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• 12-02-12 17:16Course Description (U.Crete, CS-121) Page 1 of 4http://www.csd.uoc.gr/~hy121/12a/intro.html
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• 12-02-28 21:37Exercise 5: Compare and Branch Instr. (U.Crete, CS-225) Page 1 of 3http://www.ics.forth.gr/~kateveni/225/12a/ex05_cmp_br.html
• 12-02-17 08:00Exercise 3: Memory Accesses (U.Crete, CS-225) Page 1 of 4http://www.ics.forth.gr/~kateveni/225/12a/ex03_mem.html
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• 12-02-13 01:00Course Description (U.Crete, CS-225) Page 1 of 2http://www.ics.forth.gr/~kateveni/225/12a/intro.html
• 12-02-13 00:58Exercise 1: SPIM Introduction (U.Crete, CS-225) Page 1 of 6http://www.ics.forth.gr/~kateveni/225/12a/ex01_spim.html
• 11-10-20 21:58Lab 4: Boolean Algebra, RAM (U.Crete, CS-120) Page 1 of 12http://www.csd.uoc.gr/~hy120/11f/lab04_karn_ram.html
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• 12-02-12 17:10Lab 1: Basic Equipment and Resistors (U.Crete, CS-121) Page 1 of 4http://www.csd.uoc.gr/~hy121/12a/lab01_intro.html
• 12-03-06 21:03Lectures 6: Procedure Calls, Recursion (U.Crete, CS-225) Page 1 of 3http://www.ics.forth.gr/~kateveni/225/12a/ex06_call.html
• 11-12-15 22:48Lab 12: Branches and Pointers (U.Crete, CS-120) Page 1 of 10http://www.csd.uoc.gr/~hy120/11f/lab12_br_ptr.html
• 11-10-11 18:52Lab 2: Relays, Muxes, Feedback (U.Crete, CS-120) Page 1 of 10http://www.csd.uoc.gr/~hy120/11f/lab02_relays.html
• 12-02-14 19:18Exercise 2: SPIM I/O and Loops (U.Crete, CS-225) Page 1 of 3http://www.ics.forth.gr/~kateveni/225/12a/ex02_loops.html
• 11-09-25 17:13Lab 0: Breadboard, LED, Switch Introduction (U.Crete, CS-120) Page 1 of 6http://www.csd.uoc.gr/~hy120/11f/lab00_switches.html
• 11-11-15 19:34Lab 7: Latches & Clocks (U.Crete, CS-120) Page 1 of 6http://www.csd.uoc.gr/~hy120/11f/lab07_ff.html
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• 11-10-30 20:22Lab 5: Binary Numbers, Addition (U.Crete, CS-120) Page 1 of 8http://www.csd.uoc.gr/~hy120/11f/lab05_add.html
• 11-11-18 21:38Lab 8: Counter, Edge-Triggering (U.Crete, CS-120) Page 1 of 8http://www.csd.uoc.gr/~hy120/11f/lab08_edge.html
• 11-12-09 19:08Lab 11: Datapath of a simple Processor (U.Crete, CS-120) Page 1 of 12http://www.csd.uoc.gr/~hy120/11f/lab11_dpath.html
• 11-09-27 17:44Lab 1: Logic with Switches (U.Crete, CS-120) Page 1 of 10http://www.csd.uoc.gr/~hy120/11f/lab01_swLogic.html
• 11-12-02 17:22Lab 10: FSM (U.Crete, CS-120) Page 1 of 8http://www.csd.uoc.gr/~hy120/11f/lab10_fsm.html
• 11-09-25 18:44Course Description (U.Crete, CS-120) Page 1 of 4http://www.csd.uoc.gr/~hy120/11f/intro.html
• 11-11-24 19:30Lab 9: Tri-State Buses, SRAM (U.Crete, CS-120) Page 1 of 7http://www.csd.uoc.gr/~hy120/11f/lab09_3st.html
• 11-10-14 21:14Lab 3: Comb. Logic, Gates, IC's (U.Crete, CS-120) Page 1 of 10http://www.csd.uoc.gr/~hy120/11f/lab03_combIC.html
• 12-02-21 21:07Exercise 4: Machine Lang., Instr. Formats (U.Crete, CS-225) Page 1 of 2http://www.ics.forth.gr/~kateveni/225/12a/ex04_formats.html