- CCECE 2003 -CCGEI 2003, Montral, May/mai 2003 0-7803-7781-8/03/$17.00 2003 IEEE
- Implementational Issues for Verifying RISC Pipeline Conflicts in HOL
- Modeling and Verification of Embedded Systems using Cadence SMV
- Properties Coverification for HW/SW Systems Mostafa Azizi1
- Micronet Annual Workshop 2004 Automaton based Model Checking Using Multiway Decision Graphs
- Combined Multistage Interference Cancellation and Multipath Decorrelating Techniques for Asynchronous QPSK/DS/CDMA over Multipath Rayleigh Fading
- Importing MDG Verification Results into HOL Haiyan Xiong 1 , Paul Curzon 1 , and Sofi`ene Tahar 2
- Adaptive Multistage Parallel Interference Cancellation Guoqiang Xue, Jianfeng Weng, Tho Le-Ngoc and Sofkne Tahar
- Veri cation of the MDG Components Library Paul Curzon 1 , So ene Tahar 2 , and Otmane A t Mohamed 3
- Modeling SystemC Fixed-Point Arithmetic in Behzad Akbarpour and So ene Tahar
- Modeling and Formal Verification of a Commercial Microcontroller for Embedded System Applications
- On the Verification and Reimplementation of an ATM Switch Fabric Using VIS
- IP Watermarking Techniques: Survey and Comparison
- Formal Verification of ASM Designs using the MDG Tool Amjad Gawanmeh, Sofiene Tahar
- GLSVLSI96 Draft dated of 23.9.98 Model Checking of the Fairisle ATM Switch
- Formal Hardware Veri cation by Integrating HOL and MDG V.K. Pisini 1 , S. Tahar 1 , P. Curzon 2 , O. Ait-Mohamed 3 and X. Song 4
- A Case Study on Model Checking and Refinement of Abstract State Machines
- 956 IEEE TRANSACTIONS ON COMPUTER-AIDED DESIGN OF INTEGRATED CIRCUITS AND SYSTEMS, VOL. 18, NO. 7, JULY 1999 Modeling and Formal Verification of the Fairisle
- On the Modeling and Verification of a Telecom System Block Using MDGs
- Design and Synthesis of an IEEE-754 Exponential Function
- Blind Adaptive Minimum Output Energy Rake Receiver for DS/CDMA over Multipath Fading Channels
- A Comparison of MDG and HOL for Hardware Verification
- An Analytical Model for Performance Evaluation of Multistage Parallel Interference Cancellation Detectors
- MODELING AND VERIFICATION OF AN ATM PORT CONTROLLER IN VIS
- Formal Verification of the Island Tunnel Controller using Multiway Decision Graphs
- GLSVLSI96 Draft dated of 6.10.99 Model Checking of the Fairisle ATM Switch
- On the Modeling and Verification of a Telecom System Block Using MDGs
- Middlesex University School of Computing Science
- Multistage Interference Cancellation with Diversity Reception for QPSK Asynchronous DS/CDMA System
- Practical Approaches to the Automatic Verification of an ATM Switch Fabric Using VIS
- FORMAL VERIFICATION OF AN SOC PLATFORM PROTOCOL CONVERTER Jounaidi Ben Hassen and Sofi`ene Tahar
- On the Extension of SystemC by SystemVerilog Assertions Ali Habibi and Soene Tahar
- Compositional Verification of a Switch Fabric from Nortel Networks
- Formal Verification of a DSP Chip Using an Iterative Approach Ali Habibi1, Sofine Tahar1 and Adel Ghazel2
- Proceedings of the 2002 IEEE Canadian Conference on Electrical & Computer Engineering
- Proceedings of the 2002 IEEE Canadian Conference on Electrical & Computer Engineering
- GLS-VLSI96 Draft dated of 29.12.01 A Progressive Methodology for the Verification of a DSP Chip
- Micronet Annual Workshop 2002 Hierarchical Approach for the Verification of an IEEE-754 Floating-Point Function
- Design and Verification of an ATM Knockout Switch Concentrator Jianping Lu and Sofine Tahar
- Hierarchical Verification of the Implementation of the IEEE-754 Table-Driven Floating-Point
- Proving Existential Theorems when Importing Results from MDG to HOL
- GLS-VLSI96 Draft dated of 9.3.01 MODEL CHECKING OF THE FAIRISLE ATM SWITCH FABRIC
- Practical Approaches to the Verification of a Telecom Megacell using FormalCheck
- ClientClientClient Access Unit
- Sequential and distributed simulations using Java Threads Mostafa Azizi
- Analysis of Multilevel-Quantized Soft-Limiting Detector for an FH-SSMA System Jian F. Weng, Guo Q. Xue, Tho Le-Ngoc, and Sofi`ene Tahar
- Multistage Interference Cancellation with Diversity Reception for QPSK Asynchronous DS/CDMA System over Multipath Fading Channels
- Multistage Interference Cancellation with Multipath Decorrelating for QPSK Asynchronous DS/CDMA System over Multipath Fading
- RTL Modeling of the RCMP Egress Routing Logic Murugesh P alanisamy and So ene T ahar
- Description and Validation of the In ternet Stream Protocol (ST2+) Using SDL/MSC
- Modeling and Verification of Leaders Agreement in the Intrusion-Tolerant Enclaves Using PVS
- Modeling and Verification of the Fairisle ATM Null Port Controller in VIS
- Model Checking of the RCMP-800 Input FIFO Jianping Lu and Sofine Tahar
- GLS-VLSI96 Draft dated of 30.4.01 Design and Verification of an ATM Knockout
- GLS-VLSI96 Draft dated of 12.4.00 Model Checking of the Transmit Master/Receive
- Modeling and Verification of Embedded Systems Using Cadence SMV
- Formal Verificaction of the ADSP-2100 Processor Using the HOL Theorem Prover
- A Hybrid Approach to Formal Veri cation Using HOL and MDG
- Multilevel Quantized Soft-Limiting Detector for an FH-SSMA System Jian F. Weng 1 , Tho Le-Ngoc 2 , Guo Q. Xue 3 , So ene Tahar 4
- Multistage Interference Cancellation with Diversity Reception for Asynchronous QPSK DS/CDMA Systems over Multipath Fading
- The Application of Formal Verification to SPW Designs Behzad Akbarpour and Sofiene Tahar
- Compositional Veri cation of IP Based Designs Hong Peng and So ene Tahar
- APractical Methodology for the Formal Verification of RISC Processors
- Syntactic Model Reduction H. Peng, Y. Mokhtari, S. Tahar
- GLS-VLSI96 Draft dated of 22.7.01 Functional Verification of a SCI-PHY Level 2 Protocol Engine
- Modeling and Veri cation of Leaders Agreement in the Intrusion-Tolerant Enclaves Using PVS
- A Formalization of a Hierarchical Model for RISC Processors
- Formal Verification of an Asynchronous MAC Layer Protocol in VIS
- Three Approaches to Hardware Verification: HOL, MDG and VIS Compared
- A Path Dependency Graph for Verilog Program Mohamed Zaki, Yassine Mokhtari and Sofi`ene Tahar
- Abstract--Advancement in the microelectronics era made it possible the integration of a complete yet complex system on a
- TableDriven FloatingPoint Exponential Function
- In this paper, a general methodology based on a hierar chical model of interpreters is presented for formally verify
- Formal Verification of the Island Tunnel Controller using Multiway Decision Graphs
- Embedding Multiway Decision Graphs in HOL Tarek Mhamdi and So ene Tahar
- On the Transformation of SystemC to AsmL Using Abstract Interpretation
- Comparison of SPIN and VIS for Protocol Verification
- An Approach to Link HOL and MDG for Hardware Verification V.K. Pisini 1 , S. Tahar 1 , O. AitMohamed 2 , P. Curzon 3 and X. Song 4
- RTL Modeling of the RCMP Egress Routing Logic Murugesh Palanisamy and Sofi`ene Tahar
- Embedding and Veri cation of an MDG-HDL Translator in Haiyan Xiong 1 , Paul Curzon 1 , So ene Tahar 2 , and Ann Blandford 1
- Formally Linking MDG and HOL Based on a Veri ed MDG System
- CCECE 2003 -CCGEI 2003, Montral, May/mai 2003 0-7803-7781-8/03/$17.00 2003 IEEE -001 -
- Multithreading-based Coverification Technique of HW/SW Systems
- GLS-VLSI96 Draft dated of 1.10.99 Model Checking of the Fairisle ATM Switch
- GLSVLSI96 Draft dated of 12.4.00 Model Checking of the Transmit Master/Receive
- Model Checking of a Real ATM Switch In this paper we present our experience on model check
- Implementing a Methodology for Formally Verifying RISC Processors in HOL *
- Hierarchical Verification Using an MDGHOL Hybrid Tool
- A Tool Converting Finite State Machine to VHDL Amr T. Abdel-Hamid, Mohamed Zaki and Sofi`ene Tahar
- Interfacing ASM with the MDG Tool Amjad Gawanmeh 1 , So ene Tahar 1 , and Kirsten Winter 2
- Adaptive Multistage Parallel Interference Cancellation Guoqiang Xue, Jianfeng Weng, Tho LeNgoc, and Sofi`ene Tahar
- GLSVLSI96 Draft dated of 30.4.01 Design and Verification of an ATM Knockout
- On the Correctness of an Intrusion-Tolerant Group Communication Protocol
- Formalization of Cadence SPW Fixed-Point Arithmetic in HOL
- GLSVLSI96 Draft dated of 30.11.97 Modeling and Automatic Formal Verification of
- Automated Verification with Abstract State Machines Using Multiway Decision Graphs
- Performance of Various Multistage Interference Cancellation Schemes for Asynchronous QPSK/DS/CDMA over Multipath
- Model Checking and Refinement of ASM Models Meral Shirazipour, Yassine Mokhtari and Sofiene Tahar
- Please Note! Manuscripts authored in LaTeX may appear
- Formal Verification of the RCMP Egress Routing Logic Palanisamy Murugesh and Sofi`ene Tahar
- Modeling and Verification of Leaders Agreement in the IntrusionTolerant Enclaves Using PVS
- An Analytical Model for Performance Evaluation of Parallel Interference Cancellers in CDMA Systems
- Nordic Journal of Computing COMPARING HOL AND MDG: A CASE STUDY ON
- Multistage Interference Cancellation with Diversity Reception for QPSK Asynchronous DS/CDMA System
- GLSVLSI96 Draft dated of 6.3.96 Behavioral Verification of an ATM Switch Fabric
- An approach translating CoD specification to be checked by UPPAAL Faez CHARFI*
- Int J STTT (2002) / Digital Object Identifier (DOI) 10.1007/s100090200073 Comparison of SPIN and VIS for protocol verification
- ISBN 968-36-7763-0 / 22-25 May 2000 ICT 2000 Two-way Broadband Satellite Access for Interactive Multimedia Services*
- Micronet Annual Workshop 2003 A Tool for Verifying ASM Models Using Multiway Decision Graphs
- 1996 Micronet Annual Workshop Verification of an ATM Switch Fabric using Multiway Decision Graphs
- Compositional Verification of an ATM Bit Error Rate Monitor Circuit
- Software Tools for Technology Transfer manuscript No. (will be inserted by the editor)
- Formal Verification of Pipeline Conflicts in RISC Processors
- Enabling Hardware Veri cation through Design Amr T. Abdel-Hamid 1 , So ene Tahar 1 , and John Harrison 2
- Micronet Annual Workshop 2000 HOL-MDG : A Hybrid Tool for Formal Verification
- The Impact of Design Changes on Verification Using MDGs M. Hasan Zobair, Sofine Tahar and Paul Curzon
- MDG Tools for the Verification of RTL Designs \Lambda Z. Zhou y X. Song y F. Corella z M. Langevin x E. Cerny y S. Tahar y
- Model Reduction Based on Value Dependency Hong Peng, Yassine Mokhtari and So ene Tahar
- Formal Veri cation of a SONET Telecom System Block
- Environment Synthesis for Compositional Model Checking Hong Peng, Yassine Mokhtari, and Sofiene Tahar
- A Hierarchical Approach to the Formal Verification of Embedded Systems Using MDGs
- Language Emptiness Checking using MDGs Fang Wang and Sofi
- Frequency Hopping CDMA: A Review \Lambda J. F. Weng, G. Q. Xue, T. LeNgoc, and S. Tahar
- Multiuser Detection Techniques: An Overview 1 Guoqiang Xue, Jianfeng Weng, Tho LeNgoc, and Sofi`ene Tahar
- In: Kropf, Th., Kumar, R. and Schmid, D. GI/ITGWorkshop Formale Methoden zum Entwurf korrekter Systeme
- SPIN vs. VIS: A Case Study on the Formal Verification of the ATMR Protocol Hong Peng, Sofiene Tahar and Ferhat Khendek
- A Survey on Compositional Verification Hong Peng and Sofi`ene Tahar
- Functional Verification of the RCMP Egress Routing Logic
- On the Formal Verification of Embedded Software Using Multiway Decision Graphs
- Modeling and Verification of Embedded Systems using Cadence SMV
- Hierarchical Verification of the Implementation of The IEEE754 TableDriven FloatingPoint Exponential
- Automating the Veri cation of Parameterized Hardware using a Hybrid Tool
